mb/intel/tglrvp: Enable DP ports for TGLRVP

TGLRVP uses DdiPort1Hpd and DdiPort1Ddc. So only enable them.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux
from pinctl driver.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ief6376ba59c77340e272923958b6b5f0a1456d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38529
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -49,6 +49,12 @@ chip soc/intel/tigerlake
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 
+	# enabling EDP in PortA
+	register "DdiPortAConfig" = "1"
+
+	register "DdiPort1Hpd" = "1"
+	register "DdiPort1Ddc" = "1"
+
 	register "SerialIoI2cMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,