soc/intel/alderlake/fsp_params.c: Fill PCI SSID parameters
Code taken from TGL base. TEST=Boot MSI PRO Z690-A WIFI DDR4 and see all devices have SSID applied Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3a6d299ec40bac8e29d06926572e375d7d835e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -863,6 +863,70 @@ static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg,
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}
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}
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static void fill_fsps_pci_ssid_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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struct device *dev;
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int i;
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/*
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* Prevent FSP from programming write-once subsystem IDs by providing
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* a custom SSID table. Must have at least one entry for the FSP to
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* use the table.
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*/
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struct svid_ssid_init_entry {
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union {
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struct {
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uint64_t reg:12; /* Register offset */
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uint64_t function:3;
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uint64_t device:5;
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uint64_t bus:8;
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uint64_t :4;
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uint64_t segment:16;
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uint64_t :16;
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};
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uint64_t segbusdevfuncregister;
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};
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struct {
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uint16_t svid;
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uint16_t ssid;
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};
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uint32_t reserved;
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};
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/*
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* The xHCI and HDA devices have RW/L rather than RW/O registers for
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* subsystem IDs and so must be written before FspSiliconInit locks
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* them with their default values.
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*/
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const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA };
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static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)];
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for (i = 0; i < ARRAY_SIZE(devfn_table); i++) {
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ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID;
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ssid_table[i].device = PCI_SLOT(devfn_table[i]);
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ssid_table[i].function = PCI_FUNC(devfn_table[i]);
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dev = pcidev_path_on_root(devfn_table[i]);
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if (dev) {
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ssid_table[i].svid = dev->subsystem_vendor;
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ssid_table[i].ssid = dev->subsystem_device;
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}
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}
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s_cfg->SiSsidTablePtr = (uintptr_t)ssid_table;
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s_cfg->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
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/*
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* Replace the default SVID:SSID value with the values specified in
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* the devicetree for the root device.
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*/
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dev = pcidev_path_on_root(SA_DEVFN_ROOT);
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s_cfg->SiCustomizedSvid = dev->subsystem_vendor;
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s_cfg->SiCustomizedSsid = dev->subsystem_device;
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/* Ensure FSP will program the registers */
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s_cfg->SiSkipSsidProgramming = 0;
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}
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static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
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struct soc_intel_alderlake_config *config)
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{
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@ -896,6 +960,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
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fill_fsps_fivr_params,
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fill_fsps_fivr_rfi_params,
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fill_fsps_acoustic_params,
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fill_fsps_pci_ssid_params,
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};
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for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)
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