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mb/google/hatch: Remove stryke mainboard 

The stryke project/mainboard never ended up being built and was
cancelled early on, therefore remove it from the tree.

Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Tim Wawrzynczak 2021-12-03 14:55:22 -07:00 committed by Patrick Georgi
parent 9eb7070bc4
commit 46dbbb67bf
8 changed files with 0 additions and 360 deletions
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2
src/mainboard/google/hatch/Kconfig
View File

@ -127,7 +127,6 @@ config MAINBOARD_PART_NUMBER
default "Palkia" if BOARD_GOOGLE_PALKIA default "Palkia" if BOARD_GOOGLE_PALKIA
default "Nightfury" if BOARD_GOOGLE_NIGHTFURY default "Nightfury" if BOARD_GOOGLE_NIGHTFURY
default "Puff" if BOARD_GOOGLE_PUFF default "Puff" if BOARD_GOOGLE_PUFF
default "Stryke" if BOARD_GOOGLE_STRYKE
default "Wyvern" if BOARD_GOOGLE_WYVERN default "Wyvern" if BOARD_GOOGLE_WYVERN
default "Dooly" if BOARD_GOOGLE_DOOLY default "Dooly" if BOARD_GOOGLE_DOOLY
default "Ambassador" if BOARD_GOOGLE_AMBASSADOR default "Ambassador" if BOARD_GOOGLE_AMBASSADOR
@ -162,7 +161,6 @@ config VARIANT_DIR
default "palkia" if BOARD_GOOGLE_PALKIA default "palkia" if BOARD_GOOGLE_PALKIA
default "nightfury" if BOARD_GOOGLE_NIGHTFURY default "nightfury" if BOARD_GOOGLE_NIGHTFURY
default "puff" if BOARD_GOOGLE_PUFF default "puff" if BOARD_GOOGLE_PUFF
default "stryke" if BOARD_GOOGLE_STRYKE
default "wyvern" if BOARD_GOOGLE_WYVERN default "wyvern" if BOARD_GOOGLE_WYVERN
default "dooly" if BOARD_GOOGLE_DOOLY default "dooly" if BOARD_GOOGLE_DOOLY
default "ambassador" if BOARD_GOOGLE_AMBASSADOR default "ambassador" if BOARD_GOOGLE_AMBASSADOR

4
src/mainboard/google/hatch/Kconfig.name
View File

@ -123,10 +123,6 @@ config BOARD_GOOGLE_SCOUT
bool "-> Scout" bool "-> Scout"
select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_GOOGLE_BASEBOARD_PUFF
config BOARD_GOOGLE_STRYKE
bool "-> Stryke"
select BOARD_GOOGLE_BASEBOARD_HATCH
config BOARD_GOOGLE_WYVERN config BOARD_GOOGLE_WYVERN
bool "-> Wyvern (CTL Chromebox CBx2)" bool "-> Wyvern (CTL Chromebox CBx2)"
select BOARD_GOOGLE_BASEBOARD_PUFF select BOARD_GOOGLE_BASEBOARD_PUFF

12
src/mainboard/google/hatch/variants/stryke/Makefile.inc
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@ -1,12 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
SPD_SOURCES = 4G_2400 # 0b000
SPD_SOURCES += empty_ddr4 # 0b001
SPD_SOURCES += 8G_2400 # 0b010
SPD_SOURCES += 8G_2666 # 0b011
SPD_SOURCES += 16G_2400 # 0b100
SPD_SOURCES += 16G_2666 # 0b101
SPD_SOURCES += 8G_3200 # 0b110
bootblock-y += gpio.c
ramstage-y += gpio.c

99
src/mainboard/google/hatch/variants/stryke/gpio.c
View File

@ -1,99 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
static const struct pad_config gpio_table[] = {
/* A22 : NC */
PAD_NC(GPP_A22, NONE),
/* A23 : NC */
PAD_NC(GPP_A23, NONE),
/* B20 : NC */
PAD_NC(GPP_B20, NONE),
/* B21 : NC */
PAD_NC(GPP_B21, NONE),
/* B22 : NC */
PAD_NC(GPP_B22, NONE),
/* C11 : NC */
PAD_NC(GPP_C11, NONE),
/* C12 : NC */
PAD_NC(GPP_C12, NONE),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */
PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
/* F11 : NC */
PAD_NC(GPP_F11, NONE),
/* F20 : NC */
PAD_NC(GPP_F20, NONE),
/* F21 : NC */
PAD_NC(GPP_F21, NONE),
/* F22 : NC */
PAD_NC(GPP_F22, NONE),
/* H3 : SPKR_PA_EN */
PAD_CFG_GPO(GPP_H3, 0, DEEP),
/* H19 : MEM_STRAP_0 */
PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
/* H22 : MEM_STRAP_1 */
PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
};
const struct pad_config *override_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
/*
* GPIOs configured before ramstage
* Note: the Hatch platform's romstage will configure
* the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
* as inputs before it reads them, so they are not
* needed in this table.
*/
static const struct pad_config early_gpio_table[] = {
/* B15 : H1_SLAVE_SPI_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : H1_SLAVE_SPI_CLK */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
/* B17 : H1_SLAVE_SPI_MISO_R */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
/* C8 : UART_PCH_RX_DEBUG_TX */
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
/* C9 : UART_PCH_TX_DEBUG_RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
/* C14 : BT_DISABLE_L */
PAD_CFG_GPO(GPP_C14, 0, DEEP),
/* PCH_WP_OD */
PAD_CFG_GPI(GPP_C20, NONE, DEEP),
/* C21 : H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
/* C22 : EC_IN_RW_OD */
PAD_CFG_GPI(GPP_C22, NONE, DEEP),
/* C23 : WLAN_PE_RST# */
PAD_CFG_GPO(GPP_C23, 1, DEEP),
/* E1 : M2_SSD_PEDET */
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
/* E5 : SATA_DEVSLP1 */
PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
/* F2 : MEM_CH_SEL */
PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
};
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}

3
src/mainboard/google/hatch/variants/stryke/include/variant/acpi/dptf.asl
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@ -1,3 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/acpi/dptf.asl>

8
src/mainboard/google/hatch/variants/stryke/include/variant/ec.h
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@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_EC_H
#define VARIANT_EC_H
#include <baseboard/ec.h>
#endif

14
src/mainboard/google/hatch/variants/stryke/include/variant/gpio.h
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
/* Memory configuration board straps */
#define GPIO_MEM_CONFIG_0 GPP_H19
#define GPIO_MEM_CONFIG_1 GPP_H22
#define GPIO_MEM_CONFIG_2 GPP_F10
#define GPIO_MEM_CONFIG_3 GPP_F3
#endif

218
src/mainboard/google/hatch/variants/stryke/overridetree.cb
View File

@ -1,218 +0,0 @@
chip soc/intel/cannonlake
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" #Front Camera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#| GSPI1 | |
#| I2C0 | Touchpad |
#| I2C1 | Touch screen |
#| I2C4 | Audio |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
},
}"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"
device domain 0 on
device pci 02.0 on # Integrated Graphics Device
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""Left Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device usb 2.0 on end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-C Port 1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 2.1 on end
end
chip drivers/usb/acpi
register "desc" = ""Left Type-A Port""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 2.2 on end
end
chip drivers/usb/acpi
# No Type-A Port 1
device usb 2.3 off end
end
chip drivers/usb/acpi
# Unused
device usb 2.4 off end
end
chip drivers/usb/acpi
# No WWAN
device usb 2.5 off end
end
chip drivers/usb/acpi
register "desc" = ""Camera""
register "type" = "UPC_TYPE_INTERNAL"
device usb 2.6 on end
end
chip drivers/usb/acpi
# Unused
device usb 2.7 off end
end
chip drivers/usb/acpi
# Unused
device usb 2.8 off end
end
chip drivers/usb/acpi
register "desc" = ""Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)"
device usb 2.9 on end
end
chip drivers/usb/acpi
register "desc" = ""Left Type-C Port""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device usb 3.0 on end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-C Port 1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device usb 3.1 on end
end
chip drivers/usb/acpi
register "desc" = ""Left Type-A Port""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device usb 3.2 on end
end
chip drivers/usb/acpi
# No Type-A Port 1
device usb 3.3 off end
end
chip drivers/usb/acpi
# No WWAN
device usb 3.4 off end
end
chip drivers/usb/acpi
# Unused
device usb 3.5 off end
end
end
end
end # USB xHCI
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
register "wake" = "GPE0_DW0_21"
register "probed" = "1"
device i2c 15 on end
end
end # I2C #0
device pci 15.1 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
register "probed" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "reset_delay_ms" = "100"
register "reset_off_delay_ms" = "5"
register "has_power_resource" = "1"
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
register "stop_off_delay_ms" = "5"
device i2c 49 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""GDIX0000""
register "generic.desc" = ""Goodix Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "generic.reset_delay_ms" = "120"
register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
register "generic.enable_delay_ms" = "12"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
end
end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
register "name" = ""RT58""
register "desc" = ""Realtek RT5682""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
register "property_count" = "1"
# Set the jd_src to RT5668_JD1 for jack detection
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
register "property_list[0].name" = ""realtek,jd-src""
register "property_list[0].integer" = "1"
device i2c 1a on end
end
end #I2C #4
device pci 1e.3 off end # GSPI #1
device pci 1f.3 on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end # Intel HDA
end
end