diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 8c7c093245..bf46532a95 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -22,4 +22,10 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string default "Cherry" if BOARD_GOOGLE_CHERRY + +# On MT8195 the SPI flash is actually using a SPI-NOR controller with its own bus. +# The number here should be a virtual value as (SPI_BUS_NUMBER + 1). +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 7 endif diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index 4831a39500..a1aa2fd730 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += memlayout.ld +bootblock-y += bootblock.c bootblock-y += chromeos.c verstage-y += memlayout.ld diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c new file mode 100644 index 0000000000..6f61a8282b --- /dev/null +++ b/src/mainboard/google/cherry/bootblock.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +struct pad_func { + u8 pin_id; + u8 func; +}; + +#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} + +static void nor_set_gpio_pinmux(void) +{ + const struct pad_func *ptr = NULL; + + /* GPIO 140 ~ 143 */ + struct pad_func nor_pinmux[] = { + PAD_FUNC(SPIM2_CSB, SPINOR_CS), + PAD_FUNC(SPIM2_CLK, SPINOR_CK), + PAD_FUNC(SPIM2_MO, SPINOR_IO0), + PAD_FUNC(SPIM2_MI, SPINOR_IO1), + }; + + ptr = nor_pinmux; + for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) { + gpio_set_pull((gpio_t){.id = ptr[i].pin_id}, + GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); + } +} + +void bootblock_mainboard_init(void) +{ + nor_set_gpio_pinmux(); +}