GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/denverton_ns: make use of common cbmem_top_chipset 

This replaces denverton_ns's own implementation of cbmem_top_chipset and
selects the common code one.

Change-Id: Idae96aabe2807e465bb7ab0f29910757d0346ce9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36619
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2019-11-04 22:07:29 +01:00 committed by Nico Huber
parent 0cc619bedc
commit 46e68ac99a
4 changed files with 7 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/denverton_ns/Kconfig
View File

@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_PMC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
# select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_PCR

2
src/soc/intel/denverton_ns/acpi.c
View File

@ -81,7 +81,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
gnvs->pcnt = dev_count_cpu();
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = top_of_32bit_ram();
gnvs->tolm = (uintptr_t)cbmem_top();
#if CONFIG(CONSOLE_CBMEM)
/* Update the mem console pointer. */

24
src/soc/intel/denverton_ns/memmap.c
View File

@ -38,30 +38,6 @@ static inline uintptr_t system_agent_region_base(size_t reg)
return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);
}
/* Returns min power of 2 >= size */
static inline u32 power_of_2(u32 size)
{
return size ? 1 << (1 + log2(size - 1)) : 0;
}
u32 top_of_32bit_ram(void)
{
u32 iqat_region_size = 0;
u32 tseg_region_size = system_agent_region_base(TOLUD) -
system_agent_region_base(TSEGMB);
/*
* Add IQAT region size if enabled.
*/
#if CONFIG(IQAT_ENABLE)
iqat_region_size = CONFIG_IQAT_MEMORY_REGION_SIZE;
#endif
return system_agent_region_base(TOLUD) -
power_of_2(iqat_region_size + tseg_region_size);
}
void *cbmem_top_chipset(void) { return (void *)top_of_32bit_ram(); }
static inline uintptr_t smm_region_start(void)
{
return system_agent_region_base(TSEGMB);

7
src/soc/intel/denverton_ns/systemagent.c
View File

@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <console/console.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
@ -209,6 +210,7 @@ static void mc_add_dram_resources(struct device *dev)
unsigned long index;
struct resource *resource;
uint64_t mc_values[NUM_MAP_ENTRIES];
uintptr_t top_of_ram;
/* Read in the MAP registers and report their values. */
mc_read_map_entries(dev, &mc_values[0]);
@ -246,6 +248,7 @@ static void mc_add_dram_resources(struct device *dev)
* PCI_BASE_ADDRESS_0.
*/
index = 0;
top_of_ram = (uintptr_t)cbmem_top();
/* 0 - > 0xa0000 */
base_k = 0;
@ -254,12 +257,12 @@ static void mc_add_dram_resources(struct device *dev)
/* 0x100000 -> top_of_ram */
base_k = 0x100000 >> 10;
size_k = (top_of_32bit_ram() >> 10) - base_k;
size_k = (top_of_ram >> 10) - base_k;
ram_resource(dev, index++, base_k, size_k);
/* top_of_ram -> TSEG */
resource = new_resource(dev, index++);
resource->base = top_of_32bit_ram();
resource->base = top_of_ram;
resource->size = mc_values[TSEG_REG] - resource->base;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_RESERVE |