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soc/intel/icelake: correct wrong gpio SMI register base offsets 

Reference: Intel doc# 341081-002.

Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michael Niewöhner 2021-09-15 16:35:56 +02:00 committed by Patrick Georgi
parent 85610d8d86
commit 46ef536212
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/icelake/include/soc/gpio_defs.h
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@ -253,8 +253,8 @@
#define HOSTSW_OWN_REG_0 0xb0
#define GPI_INT_STS_0 0x100
#define GPI_INT_EN_0 0x110
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
#define GPI_SMI_STS_0 0x170
#define GPI_SMI_EN_0 0x190
#define GPI_NMI_STS_0 0x1b0
#define GPI_NMI_EN_0 0x1d0
#define PAD_CFG_BASE 0x600