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soc/mediatek: Move the common part of SPI drivers to common/ 

The SPI drivers can be shared by MT8183, MT8192 and MT8195.

TEST=emerge-{oak, kukui, asurada, cherry} coreboot;
     verified on Cherry P0

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Rex-BC Chen 2021-04-27 21:20:06 +08:00 committed by Hung-Te Lin
parent 0575778667
commit 47095d5ec3
8 changed files with 61 additions and 148 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/soc/mediatek/common/include/soc/spi_common.h
View File

@ -3,20 +3,11 @@
#ifndef MTK_COMMON_SPI_H #ifndef MTK_COMMON_SPI_H
#define MTK_COMMON_SPI_H #define MTK_COMMON_SPI_H
#include <device/mmio.h>
#include <soc/gpio_base.h> #include <soc/gpio_base.h>
#include <spi-generic.h> #include <spi-generic.h>
#include <types.h> #include <types.h>
enum {
SPI_CFG1_CS_IDLE_SHIFT = 0,
SPI_CFG1_PACKET_LOOP_SHIFT = 8,
SPI_CFG1_PACKET_LENGTH_SHIFT = 16,
SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT,
SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT,
SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT,
};
enum { enum {
SPI_CMD_ACT_SHIFT = 0, SPI_CMD_ACT_SHIFT = 0,
SPI_CMD_RESUME_SHIFT = 1, SPI_CMD_RESUME_SHIFT = 1,
@ -59,7 +50,24 @@ enum spi_pad_mask {
SPI_PAD_SEL_MASK = 0x3 SPI_PAD_SEL_MASK = 0x3
}; };
struct mtk_spi_regs; /* SPI peripheral register map. */
typedef struct mtk_spi_regs {
uint32_t spi_cfg0_reg;
uint32_t spi_cfg1_reg;
uint32_t spi_tx_src_reg;
uint32_t spi_rx_dst_reg;
uint32_t spi_tx_data_reg;
uint32_t spi_rx_data_reg;
uint32_t spi_cmd_reg;
uint32_t spi_status0_reg;
uint32_t spi_status1_reg;
uint32_t spi_pad_macro_sel_reg;
uint32_t spi_cfg2_reg;
uint32_t spi_tx_src_64_reg;
uint32_t spi_rx_dst_64_reg;
} mtk_spi_regs;
check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24);
struct mtk_spi_bus { struct mtk_spi_bus {
struct spi_slave slave; struct spi_slave slave;

19
src/soc/mediatek/common/spi.c
View File

@ -34,6 +34,19 @@ static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave)
return &spi_bus[slave->bus]; return &spi_bus[slave->bus];
} }
void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks,
u32 cs_ticks, unsigned int tick_dly)
{
SET32_BITFIELDS(&regs->spi_cfg0_reg, SPI_CFG_CS_HOLD, cs_ticks - 1,
SPI_CFG_CS_SETUP, cs_ticks - 1);
SET32_BITFIELDS(&GET_SCK_REG(regs), SPI_CFG_SCK_LOW, sck_ticks - 1,
SPI_CFG_SCK_HIGH, sck_ticks - 1);
SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY, tick_dly,
SPI_CFG1_CS_IDLE, cs_ticks - 1);
}
static void spi_sw_reset(struct mtk_spi_regs *regs) static void spi_sw_reset(struct mtk_spi_regs *regs)
{ {
setbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); setbits32(&regs->spi_cmd_reg, SPI_CMD_RST_EN);
@ -121,10 +134,8 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out,
else else
size = MIN(*bytes_in, *bytes_out); size = MIN(*bytes_in, *bytes_out);
clrsetbits32(&regs->spi_cfg1_reg, SET32_BITFIELDS(&regs->spi_cfg1_reg, SPI_CFG1_PACKET_LENGTH, size - 1,
SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, SPI_CFG1_PACKET_LOOP, 0);
((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) |
(0 << SPI_CFG1_PACKET_LOOP_SHIFT));
if (*bytes_out) { if (*bytes_out) {
const uint8_t *outb = (const uint8_t *)out; const uint8_t *outb = (const uint8_t *)out;

34
src/soc/mediatek/mt8173/include/soc/spi.h
View File

@ -7,32 +7,16 @@
#define SPI_BUS_NUMBER 1 #define SPI_BUS_NUMBER 1
/* SPI peripheral register map. */ #define GET_SCK_REG(x) x->spi_cfg0_reg
typedef struct mtk_spi_regs {
uint32_t spi_cfg0_reg;
uint32_t spi_cfg1_reg;
uint32_t spi_tx_src_reg;
uint32_t spi_rx_dst_reg;
uint32_t spi_tx_data_reg;
uint32_t spi_rx_data_reg;
uint32_t spi_cmd_reg;
uint32_t spi_status0_reg;
uint32_t spi_status1_reg;
uint32_t spi_pad_macro_sel_reg;
} mtk_spi_regs;
check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0)
DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8)
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 23, 16)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 24)
enum { DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
SPI_CFG0_SCK_HIGH_SHIFT = 0, DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
SPI_CFG0_SCK_LOW_SHIFT = 8, DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
SPI_CFG0_CS_HOLD_SHIFT = 16, DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
SPI_CFG0_CS_SETUP_SHIFT = 24,
};
enum {
SPI_CFG1_TICK_DLY_SHIFT = 30,
SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT,
};
#endif #endif

14
src/soc/mediatek/mt8173/spi.c
View File

@ -26,20 +26,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus,
gpio_set_mode(GPIO(MSDC2_CMD), 0); gpio_set_mode(GPIO(MSDC2_CMD), 0);
} }
void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
unsigned int tick_dly)
{
write32(&regs->spi_cfg0_reg,
((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) |
((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) |
((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK |
SPI_CFG1_TICK_DLY_MASK,
(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
}
static const struct spi_ctrlr spi_flash_ctrlr = { static const struct spi_ctrlr spi_flash_ctrlr = {
.max_xfer_size = 65535, .max_xfer_size = 65535,
.flash_probe = mtk_spi_flash_probe, .flash_probe = mtk_spi_flash_probe,

39
src/soc/mediatek/mt8183/include/soc/spi.h
View File

@ -7,39 +7,18 @@
#define SPI_BUS_NUMBER 6 #define SPI_BUS_NUMBER 6
/* SPI peripheral register map. */ #define GET_SCK_REG(x) x->spi_cfg2_reg
typedef struct mtk_spi_regs {
uint32_t spi_cfg0_reg;
uint32_t spi_cfg1_reg;
uint32_t spi_tx_src_reg;
uint32_t spi_rx_dst_reg;
uint32_t spi_tx_data_reg;
uint32_t spi_rx_data_reg;
uint32_t spi_cmd_reg;
uint32_t spi_status0_reg;
uint32_t spi_status1_reg;
uint32_t spi_pad_macro_sel_reg;
uint32_t spi_cfg2_reg;
uint32_t spi_tx_src_64_reg;
uint32_t spi_rx_dst_64_reg;
} mtk_spi_regs;
check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
enum { DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0)
SPI_CFG0_CS_HOLD_SHIFT = 0, DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
SPI_CFG0_CS_SETUP_SHIFT = 16,
};
enum { DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
SPI_CFG2_SCK_LOW_SHIFT = 0, DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
SPI_CFG2_SCK_HIGH_SHIFT = 16, DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
}; DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
enum {
SPI_CFG1_TICK_DLY_SHIFT = 29,
SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT,
};
#endif #endif

17
src/soc/mediatek/mt8183/spi.c
View File

@ -103,23 +103,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
} }
void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
unsigned int tick_dly)
{
write32(&regs->spi_cfg0_reg,
((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
write32(&regs->spi_cfg2_reg,
((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
SPI_CFG1_CS_IDLE_MASK,
(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
}
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{ {
.ctrlr = &spi_ctrlr, .ctrlr = &spi_ctrlr,

39
src/soc/mediatek/mt8192/include/soc/spi.h
View File

@ -7,38 +7,17 @@
#define SPI_BUS_NUMBER 8 #define SPI_BUS_NUMBER 8
/* SPI peripheral register map. */ #define GET_SCK_REG(x) x->spi_cfg2_reg
typedef struct mtk_spi_regs {
uint32_t spi_cfg0_reg;
uint32_t spi_cfg1_reg;
uint32_t spi_tx_src_reg;
uint32_t spi_rx_dst_reg;
uint32_t spi_tx_data_reg;
uint32_t spi_rx_data_reg;
uint32_t spi_cmd_reg;
uint32_t spi_status0_reg;
uint32_t spi_status1_reg;
uint32_t spi_pad_macro_sel_reg;
uint32_t spi_cfg2_reg;
uint32_t spi_tx_src_64_reg;
uint32_t spi_rx_dst_64_reg;
} mtk_spi_regs;
check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
enum { DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0)
SPI_CFG0_CS_HOLD_SHIFT = 0, DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16)
SPI_CFG0_CS_SETUP_SHIFT = 16,
};
enum { DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
SPI_CFG2_SCK_LOW_SHIFT = 0, DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
SPI_CFG2_SCK_HIGH_SHIFT = 16, DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16)
}; DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29)
enum {
SPI_CFG1_TICK_DLY_SHIFT = 29,
SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT,
};
#endif #endif

17
src/soc/mediatek/mt8192/spi.c
View File

@ -112,23 +112,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
} }
void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
unsigned int tick_dly)
{
write32(&regs->spi_cfg0_reg,
((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
write32(&regs->spi_cfg2_reg,
((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
SPI_CFG1_CS_IDLE_MASK,
(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
}
static const struct spi_ctrlr spi_flash_ctrlr = { static const struct spi_ctrlr spi_flash_ctrlr = {
.max_xfer_size = 65535, .max_xfer_size = 65535,
.flash_probe = mtk_spi_flash_probe, .flash_probe = mtk_spi_flash_probe,