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mb/google/drallion: Correct USB3 OC pin configuration 

USB3 OC pin is configured for the wrong pin. Follow HW circuit
(schematics) to set it correctly.

BUG=b:147869924
TEST=USB function works well and OC function is corresponds to the
right port.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai 2020-02-14 15:50:05 +08:00 committed by Patrick Georgi
parent 4e3cb9588b
commit 4714100c49
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -154,9 +154,9 @@ chip soc/intel/cannonlake
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
register "usb3_ports[5]" = "USB3_PORT_EMPTY"