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soc/intel/elkhartlake: Update UART clock divider params 

As EHL UART source clock is 120MHz, update the clock divider
parameters (M & N) to reflect the right value.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Lean Sheng Tan 2021-07-19 01:57:16 -07:00 committed by Werner Zeh
parent 719d85bf56
commit 471dca7b10
1 changed files with 4 additions and 4 deletions
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8
src/soc/intel/elkhartlake/Kconfig
View File

@ -168,15 +168,15 @@ config CONSOLE_UART_BASE_ADDRESS
depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate
# Baudrate = (UART source clcok * M) /(N *16)
# EHL UART source clock: 100MHz
# Baudrate = (UART source clock * M) /(N *16)
# EHL UART source clock: 120MHz
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
default 0x30
default 0x25a
config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
default 0x7fff
config VBOOT
select VBOOT_SEPARATE_VERSTAGE