mb/google/rex: Add memory configuration board straps

This patch reads various memory configuration GPIOs to fill in below
details:
1. variant_memory_sku()
2. variant_is_half_populated()

BUG=b:224325352
TEST=Able to build Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I23bad8c78523cb56008e6d67e7776e57e42fbeb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-07-21 07:48:13 +00:00 committed by Martin Roth
parent 653e157eea
commit 471e24e987
2 changed files with 15 additions and 2 deletions

View file

@ -17,5 +17,11 @@
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
/* Memory configuration board straps */
#define GPIO_MEM_CONFIG_0 GPP_E11
#define GPIO_MEM_CONFIG_1 GPP_E02
#define GPIO_MEM_CONFIG_2 GPP_E01
#define GPIO_MEM_CONFIG_3 GPP_E12
#define GPIO_MEM_CH_SEL GPP_E13
#endif /* __BASEBOARD_GPIO_H__ */

View file

@ -17,12 +17,19 @@ const struct mb_cfg *__weak variant_memory_params(void)
int __weak variant_memory_sku(void)
{
return 0;
gpio_t spd_gpios[] = {
GPIO_MEM_CONFIG_0,
GPIO_MEM_CONFIG_1,
GPIO_MEM_CONFIG_2,
GPIO_MEM_CONFIG_3,
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
bool __weak variant_is_half_populated(void)
{
return 0;
return gpio_get(GPIO_MEM_CH_SEL);
}
void __weak variant_get_spd_info(struct mem_spd *spd_info)