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This patch sets max freq defaults for ddr2 and ddr3for fam10. 

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones 2011-06-03 19:59:52 +00:00 committed by Marc Jones
parent 23d3dfaa96
commit 471f103e53
6 changed files with 15 additions and 48 deletions
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12
src/northbridge/amd/amdmct/mct/mct.h
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@ -496,18 +496,6 @@ struct DCTStatStruc { /* A per Node structure*/
0=disable 0=disable
1=enable*/ 1=enable*/
#ifndef MAX_NODES_SUPPORTED
#define MAX_NODES_SUPPORTED 8
#endif
#ifndef MAX_DIMMS_SUPPORTED
#define MAX_DIMMS_SUPPORTED 8
#endif
#ifndef MAX_CS_SUPPORTED
#define MAX_CS_SUPPORTED 8
#endif
/* global function */ /* global function */
u32 NodePresent(u32 Node); u32 NodePresent(u32 Node);

17
src/northbridge/amd/amdmct/mct/mct_d.h
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@ -667,23 +667,6 @@ struct DCTStatStruc { /* A per Node structure*/
yy1b = enable with DctSelIntLvAddr set to yyb */ yy1b = enable with DctSelIntLvAddr set to yyb */
#ifndef MAX_NODES_SUPPORTED
#define MAX_NODES_SUPPORTED 8
#endif
#ifndef MAX_DIMMS_SUPPORTED
#define MAX_DIMMS_SUPPORTED 8
#endif
#ifndef MAX_CS_SUPPORTED
#define MAX_CS_SUPPORTED 8
#endif
#ifndef MCT_DIMM_SPARE_NO_WARM
#define MCT_DIMM_SPARE_NO_WARM 0
#endif
u32 Get_NB32(u32 dev, u32 reg); u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val); void Set_NB32(u32 dev, u32 reg, u32 val);
u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);

2
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -1315,7 +1315,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
u16 word; u16 word;
/* Get CPU Si Revision defined limit (NPT) */ /* Get CPU Si Revision defined limit (NPT) */
proposedFreq = 533; /* Rev F0 programmable max memclock is */ proposedFreq = 800; /* Rev F0 programmable max memclock is */
/*Get User defined limit if "limit" mode */ /*Get User defined limit if "limit" mode */
if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {

16
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
View File

@ -728,22 +728,6 @@ struct DCTStatStruc { /* A per Node structure*/
yy1b = enable with DctSelIntLvAddr set to yyb */ yy1b = enable with DctSelIntLvAddr set to yyb */
#ifndef MAX_NODES_SUPPORTED
#define MAX_NODES_SUPPORTED 8
#endif
#ifndef MAX_DIMMS_SUPPORTED
#define MAX_DIMMS_SUPPORTED 8
#endif
#ifndef MAX_CS_SUPPORTED
#define MAX_CS_SUPPORTED 8
#endif
#ifndef MCT_DIMM_SPARE_NO_WARM
#define MCT_DIMM_SPARE_NO_WARM 0
#endif
u32 Get_NB32(u32 dev, u32 reg); u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val); void Set_NB32(u32 dev, u32 reg, u32 val);
u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);

12
src/northbridge/amd/amdmct/wrappers/mcti.h
View File

@ -57,6 +57,18 @@ UPDATE AS NEEDED
#define MAX_CS_SUPPORTED 8 #define MAX_CS_SUPPORTED 8
#endif #endif
#ifndef MCT_DIMM_SPARE_NO_WARM
#define MCT_DIMM_SPARE_NO_WARM 0
#endif
#ifndef MEM_MAX_LOAD_FREQ
#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
#define MEM_MAX_LOAD_FREQ 800
#else
#define MEM_MAX_LOAD_FREQ 400
#endif
#endif
#define MCT_TRNG_KEEPOUT_START 0x00000C00 #define MCT_TRNG_KEEPOUT_START 0x00000C00
#define MCT_TRNG_KEEPOUT_END 0x00000CFF #define MCT_TRNG_KEEPOUT_END 0x00000CFF

4
src/northbridge/amd/amdmct/wrappers/mcti_d.c
View File

@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index)
//val = 200; /* 200MHz(DDR400) */ //val = 200; /* 200MHz(DDR400) */
//val = 266; /* 266MHz(DDR533) */ //val = 266; /* 266MHz(DDR533) */
//val = 333; /* 333MHz(DDR667) */ //val = 333; /* 333MHz(DDR667) */
val = 400; /* 400MHz(DDR800) */ val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */
break; break;
case NV_ECC_CAP: case NV_ECC_CAP:
#if SYSTEM_TYPE == SERVER #if SYSTEM_TYPE == SERVER
@ -237,7 +237,7 @@ static void mctHookAfterDIMMpre(void)
static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{ {
pDCTstat->PresetmaxFreq = 400; pDCTstat->PresetmaxFreq = MEM_MAX_LOAD_FREQ;
} }
#ifdef UNUSED_CODE #ifdef UNUSED_CODE