soc/fsp_broadwell_de: fix flashconsole support for platform
CB:29633 switched platform to use sb/common spi implementation, which worked until CAR_GLOBAL was removed in CB:30506. Revert the changes back to usage of CAR_GLOBAL in the common spi driver so that flashconsole will work again in romsatge for fsp_broadwell_de. Test: verify flashconsole functional on out-of-tree Broadwell-DE board Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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4721e47064
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@ -16,6 +16,7 @@
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*/
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*/
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/* This file is derived from the flashrom project. */
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/* This file is derived from the flashrom project. */
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#include <arch/early_variables.h>
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#include <stdint.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <string.h>
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@ -109,7 +110,7 @@ struct ich_spi_controller {
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uint8_t fpr_max;
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uint8_t fpr_max;
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};
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};
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static struct ich_spi_controller g_cntlr;
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static struct ich_spi_controller g_cntlr CAR_GLOBAL;
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enum {
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enum {
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SPIS_SCIP = 0x0001,
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SPIS_SCIP = 0x0001,
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@ -254,7 +255,7 @@ static void read_reg(const void *src, void *value, uint32_t size)
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static void ich_set_bbar(uint32_t minaddr)
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static void ich_set_bbar(uint32_t minaddr)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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const uint32_t bbar_mask = 0x00ffff00;
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const uint32_t bbar_mask = 0x00ffff00;
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uint32_t ichspi_bbar;
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uint32_t ichspi_bbar;
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@ -272,7 +273,7 @@ static void ich_set_bbar(uint32_t minaddr)
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void spi_init(void)
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void spi_init(void)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint8_t *rcrb; /* Root Complex Register Block */
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uint8_t *rcrb; /* Root Complex Register Block */
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uint32_t rcba; /* Root Complex Base Address */
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uint32_t rcba; /* Root Complex Base Address */
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uint8_t bios_cntl;
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uint8_t bios_cntl;
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@ -414,7 +415,7 @@ static void spi_setup_type(spi_transaction *trans)
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static int spi_setup_opcode(spi_transaction *trans)
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static int spi_setup_opcode(spi_transaction *trans)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint16_t optypes;
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uint16_t optypes;
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uint8_t opmenu[MENU_BYTES];
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uint8_t opmenu[MENU_BYTES];
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@ -494,7 +495,7 @@ static int spi_setup_offset(spi_transaction *trans)
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*/
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*/
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static int ich_status_poll(u16 bitmask, int wait_til_set)
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static int ich_status_poll(u16 bitmask, int wait_til_set)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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int timeout = 600000; /* This will result in 6 seconds */
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int timeout = 600000; /* This will result in 6 seconds */
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u16 status = 0;
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u16 status = 0;
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@ -515,7 +516,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
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static int spi_is_multichip(void)
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static int spi_is_multichip(void)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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if (!(cntlr->hsfs & HSFS_FDV))
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if (!(cntlr->hsfs & HSFS_FDV))
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return 0;
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return 0;
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return !!((cntlr->flmap0 >> 8) & 3);
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return !!((cntlr->flmap0 >> 8) & 3);
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@ -524,7 +525,7 @@ static int spi_is_multichip(void)
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static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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size_t bytesout, void *din, size_t bytesin)
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size_t bytesout, void *din, size_t bytesin)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint16_t control;
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uint16_t control;
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int16_t opcode_index;
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int16_t opcode_index;
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int with_address;
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int with_address;
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@ -674,7 +675,7 @@ spi_xfer_exit:
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/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
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/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
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static void ich_hwseq_set_addr(uint32_t addr)
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static void ich_hwseq_set_addr(uint32_t addr)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;
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uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;
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writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr);
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writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr);
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@ -687,7 +688,7 @@ static void ich_hwseq_set_addr(uint32_t addr)
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static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
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static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
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unsigned int len)
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unsigned int len)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint16_t hsfs;
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uint16_t hsfs;
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uint32_t addr;
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uint32_t addr;
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@ -727,7 +728,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
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static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
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static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
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size_t len)
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size_t len)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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u32 start, end, erase_size;
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u32 start, end, erase_size;
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int ret;
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int ret;
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uint16_t hsfc;
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uint16_t hsfc;
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@ -777,7 +778,7 @@ out:
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static void ich_read_data(uint8_t *data, int len)
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static void ich_read_data(uint8_t *data, int len)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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int i;
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int i;
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uint32_t temp32 = 0;
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uint32_t temp32 = 0;
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@ -792,7 +793,7 @@ static void ich_read_data(uint8_t *data, int len)
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static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
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static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
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void *buf)
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void *buf)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint16_t hsfc;
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uint16_t hsfc;
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uint16_t timeout = 100 * 60;
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uint16_t timeout = 100 * 60;
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uint8_t block_len;
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uint8_t block_len;
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@ -838,7 +839,7 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
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*/
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*/
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static void ich_fill_data(const uint8_t *data, int len)
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static void ich_fill_data(const uint8_t *data, int len)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint32_t temp32 = 0;
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uint32_t temp32 = 0;
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int i;
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int i;
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@ -862,7 +863,7 @@ static void ich_fill_data(const uint8_t *data, int len)
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static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
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static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
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const void *buf)
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const void *buf)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint16_t hsfc;
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uint16_t hsfc;
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uint16_t timeout = 100 * 60;
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uint16_t timeout = 100 * 60;
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uint8_t block_len;
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uint8_t block_len;
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static int spi_flash_programmer_probe(const struct spi_slave *spi,
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static int spi_flash_programmer_probe(const struct spi_slave *spi,
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struct spi_flash *flash)
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struct spi_flash *flash)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
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if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
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return spi_flash_generic_probe(spi, flash);
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return spi_flash_generic_probe(spi, flash);
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const struct region *region,
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const struct region *region,
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const enum ctrlr_prot_type type)
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const enum ctrlr_prot_type type)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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u32 start = region_offset(region);
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u32 start = region_offset(region);
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u32 end = start + region_sz(region) - 1;
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u32 end = start + region_sz(region) - 1;
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u32 reg;
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u32 reg;
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void spi_finalize_ops(void)
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void spi_finalize_ops(void)
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{
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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u16 spi_opprefix;
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u16 spi_opprefix;
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u16 optype = 0;
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u16 optype = 0;
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struct intel_swseq_spi_config spi_config = {
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struct intel_swseq_spi_config spi_config = {
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