This patch cleans up mpspec.h and allows it to be included when
HAVE_MP_TABLE=0 It also removes the artifacts from the Asus m2v-mx_se that were necessary before the change. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -1,8 +1,6 @@
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#ifndef __ASM_MPSPEC_H
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#define __ASM_MPSPEC_H
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#if HAVE_MP_TABLE==1
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/*
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* Structure definitions for SMP machines following the
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* Intel Multiprocessing Specification 1.1 and 1.4.
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@ -272,16 +270,5 @@ void *smp_write_floating_table_physaddr(unsigned long addr,
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unsigned long mpf_physptr);
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unsigned long write_smp_table(unsigned long addr);
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#else /* HAVE_MP_TABLE */
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#if 0
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static inline
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unsigned long write_smp_table(unsigned long addr)
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{
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return addr;
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}
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#endif
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#define write_smp_table(addr) (addr)
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#endif /* HAVE_MP_TABLE */
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#endif
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@ -51,9 +51,6 @@ if HAVE_ACPI_TABLES
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end
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object ./dsdt.o
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end
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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# object reset.o
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if CONFIG_USE_INIT
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makerule ./cache_as_ram_auto.o
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@ -103,7 +103,7 @@ default HAVE_FALLBACK_BOOT = 1
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default HAVE_HARD_RESET = 1
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default HAVE_PIRQ_TABLE = 0
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default IRQ_SLOT_COUNT = 11 # FIXME?
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default HAVE_MP_TABLE = 1
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default HAVE_MP_TABLE = 0
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default HAVE_OPTION_TABLE = 0 # FIXME
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# Move the default coreboot CMOS range off of AMD RTC registers.
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default LB_CKS_RANGE_START = 49
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