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soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore 

Post boot SAI PCR access to ITSS polarity regsiter is locked.
Restore of ITSS polarity does not take effect anyways. Hence
removing the related programming.

Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Aamir Bohra 2021-02-22 15:13:05 +05:30 committed by Patrick Georgi
parent a04d37ccb3
commit 4742f53770
4 changed files with 0 additions and 29 deletions
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8
src/soc/intel/alderlake/chip.c
View File

@ -127,20 +127,12 @@ static void soc_fill_gpio_pm_configuration(void)
void soc_init_pre_device(void *chip_info)
{
/* TODO: A bug has been filed, remove this W/A once FSP is updated */
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
soc_fill_gpio_pm_configuration();
/* Swap enabled PCI ports in device tree if needed. */

7
src/soc/intel/elkhartlake/chip.c
View File

@ -116,19 +116,12 @@ static void soc_fill_gpio_pm_configuration(void)
void soc_init_pre_device(void *chip_info)
{
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
soc_fill_gpio_pm_configuration();
/* swap enabled PCI ports in device tree if needed */

7
src/soc/intel/jasperlake/chip.c
View File

@ -122,19 +122,12 @@ static void soc_fill_gpio_pm_configuration(void)
void soc_init_pre_device(void *chip_info)
{
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
soc_fill_gpio_pm_configuration();
/* swap enabled PCI ports in device tree if needed */

7
src/soc/intel/tigerlake/chip.c
View File

@ -127,19 +127,12 @@ static void soc_fill_gpio_pm_configuration(void)
void soc_init_pre_device(void *chip_info)
{
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
* default policy that doesn't honor boards' requirements. */
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
soc_fill_gpio_pm_configuration();
/* Swap enabled PCI ports in device tree if needed. */