AMD Trinity boards: Add reserved memory area for SPI base address in ACPI
- SPI controller base address gets overwritten by SD controller under Linux. - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't get automatically reserved. Solution is to add it as a reserved memory area in ACPI. - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this platform was made as part of: http://review.coreboot.org/#/c/3167/3 - Once approved a follow-on patch for other southbridges using a non-standard BAR for the spi controller. Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/3270 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -1251,6 +1251,33 @@ DefinitionBlock (
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* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
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} */ /* End Method(_SB.SBRDG._INI) */
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OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
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Field(CFG,DWordAcc,NoLock,Preserve){
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Offset(0xA0),
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BAR,32} // SPI Controller Base Address Register (Index 0xA0)
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Device(LDRC) // LPC device: Resource consumption
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{
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Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
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Name (CRS, ResourceTemplate () // Current Motherboard resources
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{
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Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
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0x00000000, // Address Base
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0x00000000, // Address Length
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BAR0 // Descriptor Name
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)
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})
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Method(_CRS,0,NotSerialized)
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{
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CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
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CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
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Store(BAR,SPIB) // SPI base address mapped
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Store(0x1000,SPIL) // 4k space mapped
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Return(CRS)
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}
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}
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/* Real Time Clock Device */
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Device(RTC0) {
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Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
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@ -1242,6 +1242,33 @@ DefinitionBlock (
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* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
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} */ /* End Method(_SB.SBRDG._INI) */
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OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
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Field(CFG,DWordAcc,NoLock,Preserve){
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Offset(0xA0),
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BAR,32} // SPI Controller Base Address Register (Index 0xA0)
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Device(LDRC) // LPC device: Resource consumption
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{
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Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
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Name (CRS, ResourceTemplate () // Current Motherboard resources
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{
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Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
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0x00000000, // Address Base
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0x00000000, // Address Length
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BAR0 // Descriptor Name
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)
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})
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Method(_CRS,0,NotSerialized)
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{
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CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
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CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
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Store(BAR,SPIB) // SPI base address mapped
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Store(0x1000,SPIL) // 4k space mapped
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Return(CRS)
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}
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}
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/* Real Time Clock Device */
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Device(RTC0) {
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Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
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@ -1235,6 +1235,33 @@ DefinitionBlock (
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* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
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} */ /* End Method(_SB.SBRDG._INI) */
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OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
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Field(CFG,DWordAcc,NoLock,Preserve){
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Offset(0xA0),
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BAR,32} // SPI Controller Base Address Register (Index 0xA0)
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Device(LDRC) // LPC device: Resource consumption
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{
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Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
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Name (CRS, ResourceTemplate () // Current Motherboard resources
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{
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Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
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0x00000000, // Address Base
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0x00000000, // Address Length
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BAR0 // Descriptor Name
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)
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})
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Method(_CRS,0,NotSerialized)
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{
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CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
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CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
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Store(BAR,SPIB) // SPI base address mapped
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Store(0x1000,SPIL) // 4k space mapped
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Return(CRS)
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}
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}
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/* Real Time Clock Device */
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Device(RTC0) {
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Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
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