mb/google/brya/var/nissa: set tcc_offset value to 10

Set tcc_offset value to 10 in devicetree for Thermal Control Circuit
(TCC) activation feature as mentioned in doc #572349.

BUG=b:229804441
BRANCH=None
TEST=Build FW and test on Nivviks board

Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb

@@ -25,6 +25,8 @@ chip soc/intel/alderlake
 	# DPTF enable
 	register "dptf_enable" = "1"
 
+	register "tcc_offset" = "10"     # TCC of 90
+
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"