soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common location

Move flush_l1d_l2 function to common location within the SoC.

BUG=None:
BRANCH=None
TEST= Build for glkrvp.

Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/apollolake/car.c

@@ -20,19 +20,13 @@
 #include <cpu/x86/msr.h>
 #include <intelblocks/msr.h>
 #include <program_loading.h>
+#include <soc/cpu.h>
 
 /*
  * This file supports the necessary hoops one needs to jump through since
  * early FSP component and early stages are running from cache-as-ram.
  */
 
-static void flush_l1d_to_l2(void)
-{
-	msr_t msr = rdmsr(MSR_POWER_MISC);
-	msr.lo |= FLUSH_DL1_L2;
-	wrmsr(MSR_POWER_MISC, msr);
-}
-
 static inline int is_car_addr(uintptr_t addr)
 {
 	return ((addr >= CONFIG_DCACHE_RAM_BASE) &&

src/soc/intel/apollolake/include/soc/cpu.h

@@ -18,6 +18,9 @@
 #ifndef _SOC_APOLLOLAKE_CPU_H_
 #define _SOC_APOLLOLAKE_CPU_H_
 
+#include <cpu/x86/msr.h>
+#include <intelblocks/msr.h>
+
 /* Common Timer Copy (CTC) frequency - 19.2MHz. */
 #define CTC_FREQ		19200000
 
@@ -25,4 +28,11 @@ struct device;
 void apollolake_init_cpus(struct device *dev);
 void mainboard_devtree_update(struct device *dev);
 
+/* Flush L1D to L2 */
+static inline void flush_l1d_to_l2(void)
+{
+	msr_t msr = rdmsr(MSR_POWER_MISC);
+	msr.lo |= FLUSH_DL1_L2;
+	wrmsr(MSR_POWER_MISC, msr);
+}
 #endif /* _SOC_APOLLOLAKE_CPU_H_ */