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arch: armv7: Fix cache sync instructions. 

When the i-cache is on and the d-cache is off, the L1 i-cache is still
fetching information through L2 cache.
Since L2 cache is never invalidated, it has stale information.

BRANCH=storm
BUG=none
TEST=Resolves the invalidate data fetch from i-cache while jumping from
bootblock to romstage.

Change-Id: Ibaca1219be2e40ce5bbbd1c124863d0ea71d0466
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a13e20f9b242d8193dcb314a2bdc708c6bdfea51
Original-Change-Id: I252682d372bd505f525f075461b327e4bcf70a1a
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236422
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9587
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Deepa Dinamani 2014-12-17 13:40:43 -08:00 committed by Patrick Georgi
parent 28a269abbd
commit 47722957a1
1 changed files with 9 additions and 1 deletions
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10
src/arch/arm/armv7/cache.c
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@ -142,7 +142,15 @@ void dcache_mmu_enable(void)
void cache_sync_instructions(void) void cache_sync_instructions(void)
{ {
dcache_clean_all(); /* includes trailing DSB (in assembly) */ uint32_t sctlr;
sctlr = read_sctlr();
if (sctlr & SCTLR_C)
dcache_clean_all();
else if (sctlr & SCTLR_I)
dcache_clean_invalidate_all();
iciallu(); /* includes BPIALLU (architecturally) */ iciallu(); /* includes BPIALLU (architecturally) */
dsb(); dsb();
isb(); isb();