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soc/intel/apollolake: Use consistent convention for community names 

Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for GPIO
community names, follow one single convention. This allows for re-using
macros easily.

Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16353
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2016-08-29 22:51:41 -07:00
parent 079feec561
commit 477bc97ba0
3 changed files with 21 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/apollolake/acpi/gpio.asl
View File

@ -38,7 +38,7 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized) Method (_CRS, 0x0, NotSerialized)
{ {
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
ShiftLeft (GPIO_NORTH, 16, Local0) ShiftLeft (GPIO_N, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF) Return (^RBUF)
} }
@ -69,7 +69,7 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized) Method (_CRS, 0x0, NotSerialized)
{ {
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
ShiftLeft (GPIO_NORTHWEST, 16, Local0) ShiftLeft (GPIO_NW, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF) Return (^RBUF)
} }
@ -100,7 +100,7 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized) Method (_CRS, 0x0, NotSerialized)
{ {
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
ShiftLeft (GPIO_WEST, 16, Local0) ShiftLeft (GPIO_W, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF) Return (^RBUF)
} }
@ -131,7 +131,7 @@ scope (\_SB) {
Method (_CRS, 0x0, NotSerialized) Method (_CRS, 0x0, NotSerialized)
{ {
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
ShiftLeft (GPIO_SOUTHWEST, 16, Local0) ShiftLeft (GPIO_SW, 16, Local0)
Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS)
Return (^RBUF) Return (^RBUF)
} }

24
src/soc/intel/apollolake/gpio.c
View File

@ -31,25 +31,25 @@ static const struct pad_community {
const char *grp_name; const char *grp_name;
} gpio_communities[] = { } gpio_communities[] = {
{ {
.port = GPIO_SOUTHWEST, .port = GPIO_SW,
.first_pad = SW_OFFSET, .first_pad = SW_OFFSET,
.num_gpi_regs = NUM_SW_GPI_REGS, .num_gpi_regs = NUM_SW_GPI_REGS,
.gpi_offset = 0, .gpi_offset = 0,
.grp_name = "GPIO_GPE_SW", .grp_name = "GPIO_GPE_SW",
}, { }, {
.port = GPIO_WEST, .port = GPIO_W,
.first_pad = W_OFFSET, .first_pad = W_OFFSET,
.num_gpi_regs = NUM_W_GPI_REGS, .num_gpi_regs = NUM_W_GPI_REGS,
.gpi_offset = NUM_SW_GPI_REGS, .gpi_offset = NUM_SW_GPI_REGS,
.grp_name = "GPIO_GPE_W", .grp_name = "GPIO_GPE_W",
}, { }, {
.port = GPIO_NORTHWEST, .port = GPIO_NW,
.first_pad = NW_OFFSET, .first_pad = NW_OFFSET,
.num_gpi_regs = NUM_NW_GPI_REGS, .num_gpi_regs = NUM_NW_GPI_REGS,
.gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS, .gpi_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
.grp_name = "GPIO_GPE_NW", .grp_name = "GPIO_GPE_NW",
}, { }, {
.port = GPIO_NORTH, .port = GPIO_N,
.first_pad = N_OFFSET, .first_pad = N_OFFSET,
.num_gpi_regs = NUM_N_GPI_REGS, .num_gpi_regs = NUM_N_GPI_REGS,
.gpi_offset = NUM_NW_GPI_REGS+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS, .gpi_offset = NUM_NW_GPI_REGS+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
@ -229,13 +229,13 @@ const char *gpio_acpi_path(gpio_t gpio_num)
const struct pad_community *comm = gpio_get_community(gpio_num); const struct pad_community *comm = gpio_get_community(gpio_num);
switch (comm->port) { switch (comm->port) {
case GPIO_NORTH: case GPIO_N:
return "\\_SB.GPO0"; return "\\_SB.GPO0";
case GPIO_NORTHWEST: case GPIO_NW:
return "\\_SB.GPO1"; return "\\_SB.GPO1";
case GPIO_WEST: case GPIO_W:
return "\\_SB.GPO2"; return "\\_SB.GPO2";
case GPIO_SOUTHWEST: case GPIO_SW:
return "\\_SB.GPO3"; return "\\_SB.GPO3";
} }
@ -247,13 +247,13 @@ uint16_t gpio_acpi_pin(gpio_t gpio_num)
const struct pad_community *comm = gpio_get_community(gpio_num); const struct pad_community *comm = gpio_get_community(gpio_num);
switch (comm->port) { switch (comm->port) {
case GPIO_NORTH: case GPIO_N:
return PAD_N(gpio_num); return PAD_N(gpio_num);
case GPIO_NORTHWEST: case GPIO_NW:
return PAD_NW(gpio_num); return PAD_NW(gpio_num);
case GPIO_WEST: case GPIO_W:
return PAD_W(gpio_num); return PAD_W(gpio_num);
case GPIO_SOUTHWEST: case GPIO_SW:
return PAD_SW(gpio_num); return PAD_SW(gpio_num);
} }

10
src/soc/intel/apollolake/include/soc/gpio_defs.h
View File

@ -130,11 +130,11 @@
#define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8)) #define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8))
/* IOSF port numbers for GPIO comminuties*/ /* IOSF port numbers for GPIO comminuties*/
#define GPIO_SOUTHWEST 0xc0 #define GPIO_SW 0xc0
#define GPIO_SOUTH 0xc2 #define GPIO_S 0xc2
#define GPIO_NORTHWEST 0xc4 #define GPIO_NW 0xc4
#define GPIO_NORTH 0xc5 #define GPIO_N 0xc5
#define GPIO_WEST 0xc7 #define GPIO_W 0xc7
#define GPI_SMI_STS_0 0x140 #define GPI_SMI_STS_0 0x140
#define GPI_SMI_EN_0 0x150 #define GPI_SMI_EN_0 0x150