fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a mess of it, by forcing a build-time error when CONFIG_POST_IO was not being set. fsp 1.0 boards ended 'select'ing this in their Kconfig. Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the "select POST_IO" from boards that have it. Instead of implementing an ad-hoc changing post code display and a delay based on port 0xed, just encode the FSP failure code in the POST code. Since FSP failure codes are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble. Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8485 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Alexandru Gagniuc
parent
cc32842194
commit
47818b4d60
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@ -29,24 +29,14 @@
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# error "CONFIG_FSP_LOC must be set."
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#endif
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#ifndef CONFIG_POST_IO
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# error "CONFIG_POST_IO must be set."
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#endif
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#if CONFIG_POST_IO
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# ifndef CONFIG_POST_IO_PORT
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# error "CONFIG_POST_IO_PORT must be set."
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# endif
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#endif
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#ifndef CONFIG_CPU_MICROCODE_CBFS_LOC
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# error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set."
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#endif
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#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
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cmp $0, %eax
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jne bisthalt
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je cache_as_ram
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mov $0xa0, %eax
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jmp .Lhlt
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cache_as_ram:
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post_code(0x20)
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@ -61,8 +51,11 @@ find_fsp_ret:
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/* Save the FSP location */
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mov %eax, %ebp
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cmp $CONFIG_FSP_LOC, %eax
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jb halt1
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je find_fsp_ok
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add $0xb0, %eax
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jmp .Lhlt
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find_fsp_ok:
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post_code(0x22)
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/* Calculate entry into FSP */
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@ -81,7 +74,11 @@ find_fsp_ret:
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CAR_init_done:
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addl $4, %esp
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cmp $0, %eax
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jne halt2
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je car_init_ok
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add $0xc0, %eax
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jmp .Lhlt
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car_init_ok:
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/* Save FSP_INFO_HEADER location in ebx */
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mov %ebp, %ebx
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@ -111,50 +108,11 @@ before_romstage:
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movb $0xB8, %ah
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jmp .Lhlt
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bisthalt:
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movb $0xB9, %ah
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jmp .Lhlt
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halt1:
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/*
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* Failures for postcode 0xBA - failed in find_fsp()
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*
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* Values are:
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* 0x01 - FV signature, "_FVH" not present
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* 0x02 - FFS GUID not present
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* 0x03 - FSP INFO Header not found
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* 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
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* a different location, or does it need to be?
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* 0x05 - FSP INFO Header signature "FSPH" not found
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* 0x06 - FSP Image ID is not the expected ID.
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*/
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movb $0xBA, %ah
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jmp .Lhlt
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halt2:
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/*
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* Failures for postcode 0xBB - failed in the FSP:
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*
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* 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
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* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
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* 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
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* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
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* 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
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* 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
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*/
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movb $0xBB, %ah
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.Lhlt:
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xchg %al, %ah
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#if CONFIG_POST_IO
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#if IS_ENABLED(CONFIG_POST_IO)
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outb %al, $CONFIG_POST_IO_PORT
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#else
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post_code(POST_DEAD_CODE)
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#endif
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movl $LHLT_DELAY, %ecx
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.Lhlt_Delay:
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outb %al, $0xED
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loop .Lhlt_Delay
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hlt
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jmp .Lhlt
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/*
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@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select BOARD_ROMSIZE_KB_2048
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select POST_IO
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select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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select TSC_MONOTONIC_TIMER
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@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select BOARD_ROMSIZE_KB_2048
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select POST_IO
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select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
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select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
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select TSC_MONOTONIC_TIMER
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@ -63,10 +63,6 @@ config VIRTUAL_ROM_SIZE
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depends on ENABLE_FSP_FAST_BOOT
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default 0x800000
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config POST_IO
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bool
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default n
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config POST_DEVICE
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bool
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default n
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