mediatek/mt8183: Add RTC support
This patch implements RTC initialization. 1. initialization dcxo 2. rtc clock using dcxo 32k 3. export RTC_32K1V8_0 to SOC, export RTC_32K1V8_1 to WLAN 4. rtc register initialization 5. refactor the driver common part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Ran Bi
Patrick Georgi
parent
7bdae06170
commit
47d46d0a18
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@ -0,0 +1,105 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_MEDIATEK_RTC_COMMON_H
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#define SOC_MEDIATEK_RTC_COMMON_H
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#include <assert.h>
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#include <bcd.h>
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#include <console/console.h>
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#include <delay.h>
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#include <rtc.h>
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#include <timer.h>
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/*
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* Default values for RTC initialization
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* Year (YEA) : 1970 ~ 2037
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* Month (MTH) : 1 ~ 12
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* Day of Month (DOM): 1 ~ 31
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*/
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enum {
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RTC_DEFAULT_YEA = 2010,
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RTC_DEFAULT_MTH = 1,
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RTC_DEFAULT_DOM = 1,
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RTC_DEFAULT_DOW = 5
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};
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enum {
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RTC_2SEC_REBOOT_ENABLE = 1,
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RTC_2SEC_MODE = 2
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};
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enum {
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RTC_OSC32CON_UNLOCK1 = 0x1A57,
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RTC_OSC32CON_UNLOCK2 = 0x2B68
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};
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enum {
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RTC_PROT_UNLOCK1 = 0x586A,
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RTC_PROT_UNLOCK2 = 0x9136
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};
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enum {
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RTC_BBPU_KEY = 0x43 << 8
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};
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enum {
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RTC_IRQ_STA_AL = 1U << 0,
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RTC_IRQ_STA_TC = 1U << 1,
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RTC_IRQ_STA_LP = 1U << 3
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};
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enum {
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RTC_IRQ_EN_AL = 1U << 0,
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RTC_IRQ_EN_TC = 1U << 1,
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RTC_IRQ_EN_ONESHOT = 1U << 2,
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RTC_IRQ_EN_LP = 1U << 3,
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RTC_IRQ_EN_ONESHOT_AL = RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL
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};
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enum {
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RTC_POWERKEY1_KEY = 0xA357,
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RTC_POWERKEY2_KEY = 0x67D2
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};
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enum {
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RTC_SPAR0_32K_LESS = 1U << 6
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};
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enum {
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RTC_MIN_YEAR = 1968,
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RTC_BASE_YEAR = 1900,
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RTC_MIN_YEAR_OFFSET = RTC_MIN_YEAR - RTC_BASE_YEAR,
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RTC_NUM_YEARS = 128
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};
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enum {
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RTC_STATE_REBOOT = 0,
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RTC_STATE_RECOVER = 1,
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RTC_STATE_INIT = 2
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};
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/* external API */
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int rtc_busy_wait(void);
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int rtc_write_trigger(void);
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int rtc_writeif_unlock(void);
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void rtc_xosc_write(u16 val);
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int rtc_reg_init(void);
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u8 rtc_check_state(void);
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void rtc_boot_common(void);
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#endif /* SOC_MEDIATEK_RTC_COMMON_H */
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@ -0,0 +1,194 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/rtc_common.h>
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#include <soc/rtc.h>
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#include <soc/pmic_wrap.h>
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/* ensure rtc write success */
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int rtc_busy_wait(void)
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{
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struct stopwatch sw;
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u16 bbpu;
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stopwatch_init_usecs_expire(&sw, RTC_CBUSY_TIMEOUT_US);
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do {
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pwrap_read(RTC_BBPU, &bbpu);
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/* Time > 1sec, time out and set recovery mode enable.*/
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if (stopwatch_expired(&sw)) {
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printk(BIOS_INFO, "[RTC] BBPU CBUSY time out !!\n");
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return 0;
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}
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} while (bbpu & RTC_BBPU_CBUSY);
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return 1;
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}
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int rtc_write_trigger(void)
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{
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pwrap_write(RTC_WRTGR, 1);
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return rtc_busy_wait();
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}
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/* unlock rtc write interface */
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int rtc_writeif_unlock(void)
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{
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pwrap_write(RTC_PROT, RTC_PROT_UNLOCK1);
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if (!rtc_write_trigger())
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return 0;
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pwrap_write(RTC_PROT, RTC_PROT_UNLOCK2);
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if (!rtc_write_trigger())
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return 0;
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return 1;
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}
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/* set rtc time */
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int rtc_set(const struct rtc_time *time)
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{
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return -1;
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}
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/* get rtc time */
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int rtc_get(struct rtc_time *time)
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{
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u16 value;
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pwrap_read(RTC_TC_SEC, &value);
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time->sec = value;
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pwrap_read(RTC_TC_MIN, &value);
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time->min = value;
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pwrap_read(RTC_TC_HOU, &value);
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time->hour = value;
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pwrap_read(RTC_TC_DOM, &value);
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time->mday = value;
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pwrap_read(RTC_TC_MTH, &value);
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time->mon = value;
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pwrap_read(RTC_TC_YEA, &value);
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time->year = (value + RTC_MIN_YEAR_OFFSET) % 100;
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return 0;
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}
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/* set rtc xosc setting */
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void rtc_xosc_write(u16 val)
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{
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u16 bbpu;
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pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
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udelay(200);
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pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
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udelay(200);
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pwrap_write(RTC_OSC32CON, val);
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udelay(200);
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pwrap_read(RTC_BBPU, &bbpu);
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bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD;
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pwrap_write(RTC_BBPU, bbpu);
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rtc_write_trigger();
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}
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/* initialize rtc related registers */
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int rtc_reg_init(void)
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{
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u16 irqsta;
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pwrap_write(RTC_IRQ_EN, 0);
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pwrap_write(RTC_CII_EN, 0);
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pwrap_write(RTC_AL_MASK, 0);
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pwrap_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR);
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pwrap_write(RTC_AL_MTH, 1);
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pwrap_write(RTC_AL_DOM, 1);
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pwrap_write(RTC_AL_DOW, 4);
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pwrap_write(RTC_AL_HOU, 0);
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pwrap_write(RTC_AL_MIN, 0);
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pwrap_write(RTC_AL_SEC, 0);
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pwrap_write(RTC_DIFF, 0);
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pwrap_write(RTC_CALI, 0);
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if (!rtc_write_trigger())
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return 0;
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pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */
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/* init time counters after resetting RTC_DIFF and RTC_CALI */
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pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR);
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pwrap_write(RTC_TC_MTH, RTC_DEFAULT_MTH);
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pwrap_write(RTC_TC_DOM, RTC_DEFAULT_DOM);
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pwrap_write(RTC_TC_DOW, RTC_DEFAULT_DOW);
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pwrap_write(RTC_TC_HOU, 0);
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pwrap_write(RTC_TC_MIN, 0);
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pwrap_write(RTC_TC_SEC, 0);
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return rtc_write_trigger();
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}
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u8 rtc_check_state(void)
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{
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u16 con;
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u16 pwrky1;
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u16 pwrky2;
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pwrap_read(RTC_CON, &con);
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pwrap_read(RTC_POWERKEY1, &pwrky1);
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pwrap_read(RTC_POWERKEY2, &pwrky2);
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if (con & RTC_CON_LPSTA_RAW)
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return RTC_STATE_INIT;
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if (!rtc_busy_wait())
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return RTC_STATE_RECOVER;
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if (!rtc_writeif_unlock())
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return RTC_STATE_RECOVER;
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if (pwrky1 != RTC_POWERKEY1_KEY || pwrky2 != RTC_POWERKEY2_KEY)
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return RTC_STATE_INIT;
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else
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return RTC_STATE_REBOOT;
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}
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void rtc_boot_common(void)
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{
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u16 bbpu;
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u16 con;
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u16 irqsta;
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switch (rtc_check_state()) {
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case RTC_STATE_REBOOT:
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pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD,
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0xFFFF, 0);
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rtc_write_trigger();
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rtc_osc_init();
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break;
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case RTC_STATE_RECOVER:
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rtc_init(1);
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break;
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case RTC_STATE_INIT:
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default:
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if (!rtc_init(0))
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rtc_init(1);
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break;
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}
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pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */
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pwrap_read(RTC_BBPU, &bbpu);
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pwrap_read(RTC_CON, &con);
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printk(BIOS_INFO, "[RTC] irqsta = %x", irqsta);
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printk(BIOS_INFO, " bbpu = %#x, con = %#x\n", bbpu, con);
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}
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@ -60,7 +60,7 @@ romstage-y += memory.c
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romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
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romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c
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romstage-y += ../common/mmu_operations.c mmu_operations.c
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romstage-y += rtc.c
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romstage-y += ../common/rtc.c rtc.c
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################################################################################
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@ -77,7 +77,7 @@ ramstage-y += da9212.c
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ramstage-y += ../common/gpio.c gpio.c
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ramstage-y += ../common/wdt.c ../common/reset.c
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ramstage-y += ../common/pll.c pll.c
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ramstage-y += rtc.c
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ramstage-y += ../common/rtc.c rtc.c
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ramstage-y += ../common/usb.c usb.c
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@ -16,28 +16,10 @@
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#ifndef SOC_MEDIATEK_MT8173_RTC_H
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#define SOC_MEDIATEK_MT8173_RTC_H
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#include <soc/rtc_common.h>
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#include <stdint.h>
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#include "mt6391.h"
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/*
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* Default values for RTC initialization
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* Year (YEA) : 1970 ~ 2037
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* Month (MTH) : 1 ~ 12
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* Day of Month (DOM): 1 ~ 31
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*/
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enum {
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RTC_DEFAULT_YEA = 2010,
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RTC_DEFAULT_MTH = 1,
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RTC_DEFAULT_DOM = 1,
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RTC_DEFAULT_DOW = 5
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};
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enum {
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RTC_2SEC_REBOOT_ENABLE = 1,
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RTC_2SEC_MODE = 2
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};
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/* RTC registers */
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enum {
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RTC_BBPU = 0xE000,
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@ -88,16 +70,6 @@ enum {
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RTC_CALI = 0xE03A
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};
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enum {
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RTC_OSC32CON_UNLOCK1 = 0x1A57,
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RTC_OSC32CON_UNLOCK2 = 0x2B68
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};
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enum {
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RTC_PROT_UNLOCK1 = 0x586A,
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RTC_PROT_UNLOCK2 = 0x9136
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};
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enum {
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RTC_BBPU_PWREN = 1U << 0,
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RTC_BBPU_BBPU = 1U << 2,
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@ -109,34 +81,11 @@ enum {
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RTC_CBUSY_TIMEOUT_US = 800
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};
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enum {
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RTC_BBPU_KEY = 0x43 << 8
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};
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enum {
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RTC_IRQ_STA_AL = 1U << 0,
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RTC_IRQ_STA_TC = 1U << 1,
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RTC_IRQ_STA_LP = 1U << 3
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};
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enum {
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RTC_IRQ_EN_AL = 1U << 0,
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RTC_IRQ_EN_TC = 1U << 1,
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RTC_IRQ_EN_ONESHOT = 1U << 2,
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RTC_IRQ_EN_LP = 1U << 3,
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RTC_IRQ_EN_ONESHOT_AL = RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL
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};
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enum {
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RTC_OSC32CON_AMPEN = 1U << 8,
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RTC_OSC32CON_LNBUFEN = 1U << 11
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};
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enum {
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RTC_POWERKEY1_KEY = 0xa357,
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RTC_POWERKEY2_KEY = 0x67d2
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};
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enum {
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RTC_CON_LPEN = 1U << 2,
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RTC_CON_LPRST = 1U << 3,
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@ -161,24 +110,9 @@ enum {
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RTC_CALI_BBPU_2SEC_STAT = 1U << 11
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};
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enum {
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RTC_SPAR0_32K_LESS = 1U << 6
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};
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enum {
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RTC_MIN_YEAR = 1968,
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RTC_BASE_YEAR = 1900,
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RTC_MIN_YEAR_OFFSET = RTC_MIN_YEAR - RTC_BASE_YEAR,
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RTC_NUM_YEARS = 128
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};
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enum {
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RTC_STATE_REBOOT = 0,
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RTC_STATE_RECOVER = 1,
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RTC_STATE_INIT = 2
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};
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/* external API */
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void rtc_osc_init(void);
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int rtc_init(u8 recover);
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void rtc_boot(void);
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#endif /* SOC_MEDIATEK_MT8173_RTC_H */
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@ -13,133 +13,13 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <bcd.h>
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#include <console/console.h>
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#include <delay.h>
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#include <rtc.h>
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#include <timer.h>
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#include <soc/rtc_common.h>
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#include <soc/rtc.h>
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#include <soc/mt6391.h>
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#include <soc/pmic_wrap.h>
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#include <soc/rtc.h>
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#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8))
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/* ensure rtc write success */
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static inline int rtc_busy_wait(void)
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{
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struct stopwatch sw;
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u16 bbpu;
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stopwatch_init_usecs_expire(&sw, RTC_CBUSY_TIMEOUT_US);
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do {
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pwrap_read(RTC_BBPU, &bbpu);
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/* Time > 1sec, time out and set recovery mode enable.*/
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if (stopwatch_expired(&sw)) {
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printk(BIOS_INFO, "[RTC] BBPU CBUSY time out !!\n");
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return 0;
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}
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} while (bbpu & RTC_BBPU_CBUSY);
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return 1;
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}
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static int write_trigger(void)
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{
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pwrap_write(RTC_WRTGR, 1);
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return rtc_busy_wait();
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}
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/* unlock rtc write interface */
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static int writeif_unlock(void)
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{
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pwrap_write(RTC_PROT, RTC_PROT_UNLOCK1);
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if (!write_trigger())
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return 0;
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pwrap_write(RTC_PROT, RTC_PROT_UNLOCK2);
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if (!write_trigger())
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return 0;
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return 1;
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}
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/* set rtc time */
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int rtc_set(const struct rtc_time *time)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* get rtc time */
|
||||
int rtc_get(struct rtc_time *time)
|
||||
{
|
||||
u16 value;
|
||||
|
||||
pwrap_read(RTC_TC_SEC, &value);
|
||||
time->sec = value;
|
||||
pwrap_read(RTC_TC_MIN, &value);
|
||||
time->min = value;
|
||||
pwrap_read(RTC_TC_HOU, &value);
|
||||
time->hour = value;
|
||||
pwrap_read(RTC_TC_DOM, &value);
|
||||
time->mday = value;
|
||||
pwrap_read(RTC_TC_MTH, &value);
|
||||
time->mon = value;
|
||||
pwrap_read(RTC_TC_YEA, &value);
|
||||
time->year = (value + RTC_MIN_YEAR_OFFSET) % 100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* set rtc xosc setting */
|
||||
static void rtc_xosc_write(u16 val)
|
||||
{
|
||||
pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
|
||||
udelay(200);
|
||||
pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
|
||||
udelay(200);
|
||||
|
||||
pwrap_write(RTC_OSC32CON, val);
|
||||
udelay(200);
|
||||
pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
|
||||
write_trigger();
|
||||
}
|
||||
|
||||
/* initialize rtc related registers */
|
||||
static int rtc_reg_init(void)
|
||||
{
|
||||
u16 irqsta;
|
||||
|
||||
pwrap_write(RTC_IRQ_EN, 0);
|
||||
pwrap_write(RTC_CII_EN, 0);
|
||||
pwrap_write(RTC_AL_MASK, 0);
|
||||
pwrap_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR);
|
||||
pwrap_write(RTC_AL_MTH, 1);
|
||||
pwrap_write(RTC_AL_DOM, 1);
|
||||
pwrap_write(RTC_AL_DOW, 4);
|
||||
pwrap_write(RTC_AL_HOU, 0);
|
||||
pwrap_write(RTC_AL_MIN, 0);
|
||||
pwrap_write(RTC_AL_SEC, 0);
|
||||
|
||||
pwrap_write(RTC_DIFF, 0);
|
||||
pwrap_write(RTC_CALI, 0);
|
||||
if (!write_trigger())
|
||||
return 0;
|
||||
|
||||
pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */
|
||||
|
||||
/* init time counters after resetting RTC_DIFF and RTC_CALI */
|
||||
pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR);
|
||||
pwrap_write(RTC_TC_MTH, RTC_DEFAULT_MTH);
|
||||
pwrap_write(RTC_TC_DOM, RTC_DEFAULT_DOM);
|
||||
pwrap_write(RTC_TC_DOW, RTC_DEFAULT_DOW);
|
||||
pwrap_write(RTC_TC_HOU, 0);
|
||||
pwrap_write(RTC_TC_MIN, 0);
|
||||
pwrap_write(RTC_TC_SEC, 0);
|
||||
|
||||
return write_trigger();
|
||||
}
|
||||
|
||||
/* initialize rtc related gpio */
|
||||
static int rtc_gpio_init(void)
|
||||
|
|
@ -155,11 +35,11 @@ static int rtc_gpio_init(void)
|
|||
con |= (RTC_CON_GPEN | RTC_CON_GOE);
|
||||
con &= ~(RTC_CON_F32KOB);
|
||||
pwrap_write(RTC_CON, con);
|
||||
return write_trigger();
|
||||
return rtc_write_trigger();
|
||||
}
|
||||
|
||||
/* set xosc mode */
|
||||
static void rtc_osc_init(void)
|
||||
void rtc_osc_init(void)
|
||||
{
|
||||
u16 con;
|
||||
|
||||
|
|
@ -176,26 +56,26 @@ static void rtc_osc_init(void)
|
|||
static int rtc_lpd_init(void)
|
||||
{
|
||||
pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
|
||||
if (!write_trigger())
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0);
|
||||
if (!write_trigger())
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0);
|
||||
if (!write_trigger())
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* rtc init check */
|
||||
static int rtc_init(u8 recover)
|
||||
int rtc_init(u8 recover)
|
||||
{
|
||||
printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover);
|
||||
|
||||
if (!writeif_unlock())
|
||||
if (!rtc_writeif_unlock())
|
||||
return 0;
|
||||
|
||||
if (!rtc_gpio_init())
|
||||
|
|
@ -213,7 +93,7 @@ static int rtc_init(u8 recover)
|
|||
/* write powerkeys */
|
||||
pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
|
||||
pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
|
||||
if (!write_trigger())
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
if (recover)
|
||||
|
|
@ -238,8 +118,8 @@ static void rtc_bbpu_power_on(void)
|
|||
/* pull PWRBB high */
|
||||
bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_BBPU | RTC_BBPU_PWREN;
|
||||
pwrap_write(RTC_BBPU, bbpu);
|
||||
ret = write_trigger();
|
||||
printk(BIOS_INFO, "[RTC] %s write_trigger=%d\n", __func__, ret);
|
||||
ret = rtc_write_trigger();
|
||||
printk(BIOS_INFO, "[RTC] %s rtc_write_trigger=%d\n", __func__, ret);
|
||||
|
||||
/* enable DCXO to transform external 32KHz clock to 26MHz clock
|
||||
directly sent to SoC */
|
||||
|
|
@ -256,63 +136,12 @@ static void rtc_bbpu_power_on(void)
|
|||
pwrap_write_field(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
|
||||
}
|
||||
|
||||
static u8 rtc_check_state(void)
|
||||
{
|
||||
u16 con;
|
||||
u16 pwrky1;
|
||||
u16 pwrky2;
|
||||
|
||||
pwrap_read(RTC_CON, &con);
|
||||
pwrap_read(RTC_POWERKEY1, &pwrky1);
|
||||
pwrap_read(RTC_POWERKEY2, &pwrky2);
|
||||
|
||||
if (con & RTC_CON_LPSTA_RAW)
|
||||
return RTC_STATE_INIT;
|
||||
|
||||
if (!rtc_busy_wait())
|
||||
return RTC_STATE_RECOVER;
|
||||
|
||||
if (!writeif_unlock())
|
||||
return RTC_STATE_RECOVER;
|
||||
|
||||
if (pwrky1 != RTC_POWERKEY1_KEY || pwrky2 != RTC_POWERKEY2_KEY)
|
||||
return RTC_STATE_INIT;
|
||||
else
|
||||
return RTC_STATE_REBOOT;
|
||||
}
|
||||
|
||||
/* the rtc boot flow entry */
|
||||
void rtc_boot(void)
|
||||
{
|
||||
u16 bbpu;
|
||||
u16 con;
|
||||
u16 irqsta;
|
||||
|
||||
pwrap_write(PMIC_RG_TOP_CKPDN, 0);
|
||||
pwrap_write(PMIC_RG_TOP_CKPDN2, 0);
|
||||
|
||||
switch (rtc_check_state()) {
|
||||
case RTC_STATE_REBOOT:
|
||||
pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0,
|
||||
0);
|
||||
write_trigger();
|
||||
rtc_osc_init();
|
||||
break;
|
||||
case RTC_STATE_RECOVER:
|
||||
rtc_init(1);
|
||||
break;
|
||||
case RTC_STATE_INIT:
|
||||
default:
|
||||
if (!rtc_init(0))
|
||||
rtc_init(1);
|
||||
break;
|
||||
}
|
||||
|
||||
pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */
|
||||
pwrap_read(RTC_BBPU, &bbpu);
|
||||
pwrap_read(RTC_CON, &con);
|
||||
|
||||
printk(BIOS_INFO, "[RTC] irqsta = %x", irqsta);
|
||||
printk(BIOS_INFO, " bbpu = %#x, con = %#x\n", bbpu, con);
|
||||
rtc_boot_common();
|
||||
rtc_bbpu_power_on();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ romstage-y += mt8183.c
|
|||
romstage-y += ../common/gpio.c gpio.c
|
||||
romstage-y += ../common/mmu_operations.c mmu_operations.c
|
||||
romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
|
||||
romstage-y += ../common/rtc.c rtc.c
|
||||
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
|
||||
romstage-y += ../common/timer.c
|
||||
romstage-y += ../common/uart.c
|
||||
|
|
|
|||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 MediaTek Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SOC_MEDIATEK_MT8183_RTC_H
|
||||
#define SOC_MEDIATEK_MT8183_RTC_H
|
||||
|
||||
#include <soc/rtc_common.h>
|
||||
#include <halt.h>
|
||||
|
||||
/* RTC registers */
|
||||
enum {
|
||||
RTC_BBPU = 0x0588,
|
||||
RTC_IRQ_STA = 0x058A,
|
||||
RTC_IRQ_EN = 0x058C,
|
||||
RTC_CII_EN = 0x058E
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_TC_SEC = 0x0592,
|
||||
RTC_TC_MIN = 0x0594,
|
||||
RTC_TC_HOU = 0x0596,
|
||||
RTC_TC_DOM = 0x0598,
|
||||
RTC_TC_DOW = 0x059A,
|
||||
RTC_TC_MTH = 0x059C,
|
||||
RTC_TC_YEA = 0x059E
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_AL_SEC = 0x05A0,
|
||||
RTC_AL_MIN = 0x05A2,
|
||||
RTC_AL_HOU = 0x05A4,
|
||||
RTC_AL_DOM = 0x05A6,
|
||||
RTC_AL_DOW = 0x05A8,
|
||||
RTC_AL_MTH = 0x05AA,
|
||||
RTC_AL_YEA = 0x05AC,
|
||||
RTC_AL_MASK = 0x0590
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_OSC32CON = 0x05AE,
|
||||
RTC_CON = 0x05C4,
|
||||
RTC_WRTGR = 0x05C2
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_POWERKEY1 = 0x05B0,
|
||||
RTC_POWERKEY2 = 0x05B2
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_PDN1 = 0x05B4,
|
||||
RTC_PDN2 = 0x05B6,
|
||||
RTC_SPAR0 = 0x05B8,
|
||||
RTC_SPAR1 = 0x05BA,
|
||||
RTC_PROT = 0x05BC,
|
||||
RTC_DIFF = 0x05BE,
|
||||
RTC_CALI = 0x05C0
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_BBPU_PWREN = 1U << 0,
|
||||
RTC_BBPU_CLR = 1U << 1,
|
||||
RTC_BBPU_INIT = 1U << 2,
|
||||
RTC_BBPU_AUTO = 1U << 3,
|
||||
RTC_BBPU_CLRPKY = 1U << 4,
|
||||
RTC_BBPU_RELOAD = 1U << 5,
|
||||
RTC_BBPU_CBUSY = 1U << 6,
|
||||
|
||||
RTC_CBUSY_TIMEOUT_US = 800
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_CON_VBAT_LPSTA_RAW = 1U << 0,
|
||||
RTC_CON_EOSC32_LPEN = 1U << 1,
|
||||
RTC_CON_XOSC32_LPEN = 1U << 2,
|
||||
RTC_CON_LPRST = 1U << 3,
|
||||
RTC_CON_CDBO = 1U << 4,
|
||||
RTC_CON_F32KOB = 1U << 5,
|
||||
RTC_CON_GPO = 1U << 6,
|
||||
RTC_CON_GOE = 1U << 7,
|
||||
RTC_CON_GSR = 1U << 8,
|
||||
RTC_CON_GSMT = 1U << 9,
|
||||
RTC_CON_GPEN = 1U << 10,
|
||||
RTC_CON_GPU = 1U << 11,
|
||||
RTC_CON_GE4 = 1U << 12,
|
||||
RTC_CON_GE8 = 1U << 13,
|
||||
RTC_CON_GPI = 1U << 14,
|
||||
RTC_CON_LPSTA_RAW = 1U << 15
|
||||
};
|
||||
|
||||
enum {
|
||||
RTC_EMBCK_SRC_SEL = 1 << 8,
|
||||
RTC_EMBCK_SEL_MODE = 3 << 6,
|
||||
RTC_XOSC32_ENB = 1 << 5,
|
||||
RTC_REG_XOSC32_ENB = 1 << 15
|
||||
};
|
||||
|
||||
/* PMIC TOP Register Definition */
|
||||
enum {
|
||||
PMIC_RG_SCK_TOP_CON0 = 0x050C
|
||||
};
|
||||
|
||||
/* PMIC TOP Register Definition */
|
||||
enum {
|
||||
PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
|
||||
PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
|
||||
PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
|
||||
PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
|
||||
PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
|
||||
PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
|
||||
};
|
||||
|
||||
/* PMIC DCXO Register Definition */
|
||||
enum {
|
||||
PMIC_RG_DCXO_CW00 = 0x0788,
|
||||
PMIC_RG_DCXO_CW02 = 0x0790,
|
||||
PMIC_RG_DCXO_CW07 = 0x079A,
|
||||
PMIC_RG_DCXO_CW09 = 0x079E,
|
||||
PMIC_RG_DCXO_CW11 = 0x07A2,
|
||||
PMIC_RG_DCXO_CW13 = 0x07AA,
|
||||
PMIC_RG_DCXO_CW15 = 0x07AE,
|
||||
PMIC_RG_DCXO_CW16 = 0x07B0,
|
||||
PMIC_RG_DCXO_CW21 = 0x07BA,
|
||||
PMIC_RG_DCXO_ELR0 = 0x07C4
|
||||
};
|
||||
|
||||
enum {
|
||||
PMIC_RG_TOP_TMA_KEY = 0x03A8
|
||||
};
|
||||
|
||||
/* external API */
|
||||
void rtc_bbpu_power_on(void);
|
||||
void rtc_osc_init(void);
|
||||
int rtc_init(u8 recover);
|
||||
void rtc_boot(void);
|
||||
|
||||
#endif /* SOC_MEDIATEK_MT8183_RTC_H */
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 MediaTek Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/rtc_common.h>
|
||||
#include <soc/rtc.h>
|
||||
#include <soc/mt6358.h>
|
||||
#include <soc/pmic_wrap.h>
|
||||
|
||||
#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8))
|
||||
|
||||
/* initialize rtc setting of using dcxo clock */
|
||||
static void rtc_enable_dcxo(void)
|
||||
{
|
||||
u16 bbpu, con, osc32con, sec;
|
||||
|
||||
pwrap_read(RTC_BBPU, &bbpu);
|
||||
pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
|
||||
rtc_write_trigger();
|
||||
|
||||
mdelay(1);
|
||||
if (!rtc_writeif_unlock()) /* Unlock for reload */
|
||||
printk(BIOS_INFO,
|
||||
"[RTC] %s rtc_writeif_unlock() fail\n", __func__);
|
||||
|
||||
pwrap_read(RTC_OSC32CON, &osc32con);
|
||||
rtc_xosc_write((osc32con & ~RTC_EMBCK_SRC_SEL)
|
||||
| RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB);
|
||||
pwrap_read(RTC_BBPU, &bbpu);
|
||||
pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
|
||||
rtc_write_trigger();
|
||||
|
||||
pwrap_read(RTC_CON, &con);
|
||||
pwrap_read(RTC_OSC32CON, &osc32con);
|
||||
pwrap_read(RTC_AL_SEC, &sec);
|
||||
printk(BIOS_INFO, "[RTC] %s con = 0x%x, osc32con = 0x%x, sec = 0x%x\n",
|
||||
__func__, con, osc32con, sec);
|
||||
}
|
||||
|
||||
/* initialize rtc related gpio */
|
||||
static int rtc_gpio_init(void)
|
||||
{
|
||||
u16 con;
|
||||
|
||||
/* RTC_32K1V8 clock change from 128k div 4 source
|
||||
* to RTC 32k source
|
||||
*/
|
||||
pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3);
|
||||
|
||||
/* Export 32K clock RTC_32K1V8_1 */
|
||||
pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1);
|
||||
|
||||
/* Export 32K clock RTC_32K2V8 */
|
||||
pwrap_read(RTC_CON, &con);
|
||||
con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN);
|
||||
con |= (RTC_CON_GPEN | RTC_CON_GOE);
|
||||
con &= ~(RTC_CON_F32KOB);
|
||||
pwrap_write(RTC_CON, con);
|
||||
return rtc_write_trigger();
|
||||
}
|
||||
|
||||
/* set xosc mode */
|
||||
void rtc_osc_init(void)
|
||||
{
|
||||
/* enable 32K export */
|
||||
rtc_gpio_init();
|
||||
}
|
||||
|
||||
/* low power detect setting */
|
||||
static int rtc_lpd_init(void)
|
||||
{
|
||||
u16 con;
|
||||
|
||||
con = pwrap_read(RTC_CON, &con) | RTC_CON_XOSC32_LPEN;
|
||||
con &= ~RTC_CON_LPRST;
|
||||
pwrap_write(RTC_CON, con);
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
con |= RTC_CON_LPRST;
|
||||
pwrap_write(RTC_CON, con);
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
con &= ~RTC_CON_LPRST;
|
||||
pwrap_write(RTC_CON, con);
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
con = pwrap_read(RTC_CON, &con) | RTC_CON_EOSC32_LPEN;
|
||||
con &= ~RTC_CON_LPRST;
|
||||
pwrap_write(RTC_CON, con);
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
con |= RTC_CON_LPRST;
|
||||
pwrap_write(RTC_CON, con);
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
con &= ~RTC_CON_LPRST;
|
||||
pwrap_write(RTC_CON, con);
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static bool rtc_hw_init(void)
|
||||
{
|
||||
u16 bbpu;
|
||||
|
||||
pwrap_read(RTC_BBPU, &bbpu);
|
||||
pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT);
|
||||
rtc_write_trigger();
|
||||
|
||||
udelay(500);
|
||||
|
||||
pwrap_read(RTC_BBPU, &bbpu);
|
||||
pwrap_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
|
||||
rtc_write_trigger();
|
||||
|
||||
pwrap_read(RTC_BBPU, &bbpu);
|
||||
if (bbpu & RTC_BBPU_INIT) {
|
||||
printk(BIOS_INFO, "[RTC] %s:%d timeout\n", __func__, __LINE__);
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/* rtc init check */
|
||||
int rtc_init(u8 recover)
|
||||
{
|
||||
printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover);
|
||||
|
||||
if (!rtc_writeif_unlock())
|
||||
return 0;
|
||||
|
||||
if (!rtc_gpio_init())
|
||||
return 0;
|
||||
|
||||
/* using dcxo 32K clock */
|
||||
rtc_enable_dcxo();
|
||||
|
||||
if (recover)
|
||||
mdelay(20);
|
||||
|
||||
/* write powerkeys */
|
||||
pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
|
||||
pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
|
||||
if (!rtc_write_trigger())
|
||||
return 0;
|
||||
|
||||
if (!rtc_reg_init())
|
||||
return 0;
|
||||
if (!rtc_lpd_init())
|
||||
return 0;
|
||||
if (!rtc_hw_init())
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* enable rtc bbpu */
|
||||
void rtc_bbpu_power_on(void)
|
||||
{
|
||||
u16 bbpu;
|
||||
int ret;
|
||||
|
||||
/* pull powerhold high, control by pmic */
|
||||
pmic_set_power_hold(true);
|
||||
|
||||
/* pull PWRBB high */
|
||||
bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
|
||||
pwrap_write(RTC_BBPU, bbpu);
|
||||
ret = rtc_write_trigger();
|
||||
printk(BIOS_INFO, "[RTC] %s rtc_write_trigger=%d\n", __func__, ret);
|
||||
|
||||
pwrap_read(RTC_BBPU, &bbpu);
|
||||
printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu);
|
||||
}
|
||||
|
||||
void poweroff(void)
|
||||
{
|
||||
u16 bbpu;
|
||||
|
||||
if (!rtc_writeif_unlock())
|
||||
printk(BIOS_INFO,
|
||||
"[RTC] %s rtc_writeif_unlock() fail\n", __func__);
|
||||
/* pull PWRBB low */
|
||||
bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
|
||||
pwrap_write(RTC_BBPU, bbpu);
|
||||
|
||||
pmic_set_power_hold(false);
|
||||
halt();
|
||||
}
|
||||
|
||||
static void dcxo_init(void)
|
||||
{
|
||||
/* Buffer setting */
|
||||
pwrap_write(PMIC_RG_DCXO_CW15, 0xA2AA);
|
||||
pwrap_write(PMIC_RG_DCXO_CW13, 0x98E9);
|
||||
pwrap_write(PMIC_RG_DCXO_CW16, 0x9855);
|
||||
|
||||
/* 26M enable control */
|
||||
/* Enable clock buffer XO_SOC, XO_CEL */
|
||||
pwrap_write(PMIC_RG_DCXO_CW00, 0x4805);
|
||||
pwrap_write(PMIC_RG_DCXO_CW11, 0x8000);
|
||||
|
||||
/* Load thermal coefficient */
|
||||
pwrap_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
|
||||
pwrap_write(PMIC_RG_DCXO_CW21, 0x12A7);
|
||||
pwrap_write(PMIC_RG_DCXO_ELR0, 0xD004);
|
||||
pwrap_write(PMIC_RG_TOP_TMA_KEY, 0x0000);
|
||||
|
||||
/* Adjust OSC FPM setting */
|
||||
pwrap_write(PMIC_RG_DCXO_CW07, 0x8FFE);
|
||||
|
||||
/* Re-Calibrate OSC current */
|
||||
pwrap_write(PMIC_RG_DCXO_CW09, 0x008F);
|
||||
udelay(100);
|
||||
pwrap_write(PMIC_RG_DCXO_CW09, 0x408F);
|
||||
mdelay(5);
|
||||
}
|
||||
|
||||
/* the rtc boot flow entry */
|
||||
void rtc_boot(void)
|
||||
{
|
||||
/* dcxo clock init settings */
|
||||
dcxo_init();
|
||||
|
||||
/* dcxo 32k init settings */
|
||||
pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
|
||||
pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
|
||||
|
||||
rtc_boot_common();
|
||||
rtc_bbpu_power_on();
|
||||
}
|
||||
Loading…
Reference in New Issue