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soc/intel/apollolake: FSP Header file update for FSP 139_40 

FSP 2.0 spec has updated the signatures for the FSPM and FSPS blobs
with the 139_40 release. In order to successfully pass through
memory/silicon init the header files must be updated to the latest
versions

BUG=chrome-os-partner:52784
BRANCH=none
TEST=built and booted

Change-Id: Ib60d0d9afa4ee29dff26177826ba59db81b630e8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15066
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Brandon Breitenstein 2016-06-03 13:59:28 -07:00 committed by Aaron Durbin
parent c9bf8bfabf
commit 47d4f7cec3
3 changed files with 18 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/apollolake/include/soc/fsp/FspUpd.h
View File

@ -33,10 +33,10 @@ are permitted provided that the following conditions are met:
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
#define FSPT_UPD_SIGNATURE 0x4450555F54505346 /* 'FSPT_UPD' */
#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
#endif

6
src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
View File

@ -526,7 +526,11 @@ struct FSP_M_CONFIG {
/** Offset 0x0131
**/
uint8_t ReservedFspmUpd[31];
void* MrcBootDataPtr;
/** Offset 0x0135
**/
uint8_t ReservedFspmUpd[27];
} __attribute__((packed));
/** Fsp M Test Configuration

14
src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
View File

@ -167,10 +167,10 @@ struct FSP_S_CONFIG {
uint32_t HdaVerbTablePtr;
/** Offset 0x0039 - Enable/Disable P2SB device hidden.
Enable/Disable P2SB device hidden. 0:Disable, 1:Enable(Default).
Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
uint8_t HideP2sb;
uint8_t P2sbUnhide;
/** Offset 0x003A - IPU Enable/Disable
Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).
@ -1477,9 +1477,15 @@ struct FSP_S_CONFIG {
**/
uint8_t PcieRpSelectableDeemphasis[6];
/** Offset 0x0326
/** Offset 0x0326 - Os Selection Mode
Select OS mode. 0:Windows(default), 1:Android, 2:Win7
$EN_DIS
**/
uint8_t ReservedFspsUpd[10];
uint8_t OsSelection;
/** Offset 0x0327
**/
uint8_t ReservedFspsUpd[9];
} __attribute__((packed));
/** Fsp S Test Configuration