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cpu/x86: Link entry32.inc 

Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2020-11-22 00:55:31 +02:00
parent 404c0c455c
commit 47d58e5df0
4 changed files with 30 additions and 38 deletions
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2
src/arch/x86/Makefile.inc
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@ -85,8 +85,6 @@ bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
bootblock-y += bootblock_crt0.S
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
$(eval $(call early_x86_stage,bootblock,elf32-i386)) $(eval $(call early_x86_stage,bootblock,elf32-i386))
else else

33
src/cpu/x86/32bit/entry32.inc
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@ -1,33 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* For starting coreboot in protected mode */
#include <arch/rom_segs.h>
#include <cpu/x86/post_code.h>
.code32
/*
* When we come here we are in protected mode.
* NOTE aligned to 4 so that we are sure that the prefetch
* cache will be reloaded.
*/
.align 4
.globl __protected_start
__protected_start:
/* Save the BIST value */
movl %eax, %ebp
#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_ENTER_PROTECTED_MODE)
#endif
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw %ax, %fs
movw %ax, %gs
/* Restore the BIST value to %eax */
movl %ebp, %eax

1
src/cpu/x86/Makefile.inc
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@ -8,6 +8,7 @@ ramstage-y += backup_default_smm.c
subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm
bootblock-y += entry32.S
bootblock-y += entry16.S bootblock-y += entry16.S
bootblock-y += reset16.S bootblock-y += reset16.S

32
src/arch/x86/bootblock_crt0.S → src/cpu/x86/entry32.S
View File

@ -1,4 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
/* For starting coreboot in protected mode */
/* /*
* This is the modern bootblock. It prepares the system for C environment runtime * This is the modern bootblock. It prepares the system for C environment runtime
* setup. The actual setup is done by hardware-specific code. * setup. The actual setup is done by hardware-specific code.
@ -8,15 +11,38 @@
* *
*/ */
#include <arch/rom_segs.h>
#include <cpu/x86/cr.h> #include <cpu/x86/cr.h>
#include <cpu/x86/post_code.h>
.section .init, "ax", @progbits .section .init, "ax", @progbits
.code32
/* /*
* Include the old code for reset vector and protected mode entry. That code has * When we come here we are in protected mode.
* withstood the test of time. * NOTE aligned to 4 so that we are sure that the prefetch
* cache will be reloaded.
*/ */
#include <cpu/x86/32bit/entry32.inc> .align 4
.globl __protected_start
__protected_start:
/* Save the BIST value */
movl %eax, %ebp
#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_ENTER_PROTECTED_MODE)
#endif
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw %ax, %fs
movw %ax, %gs
/* Restore the BIST value to %eax */
movl %ebp, %eax
#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP) #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)