From 481018ad0890ac02ef187baa89beeb65af42dff5 Mon Sep 17 00:00:00 2001
From: Jon Murphy <jpmurphy@google.com>
Date: Wed, 31 May 2023 21:04:38 -0600
Subject: [PATCH] mb/google/myst: Add USB config

Add the phoenix usb config struct for Myst since the FSP has been
updated to accept the config from coreboot and the default values
do not work.

BUG=None
TEST=Boot to OS on Myst, verify devices are seen with lsusb

Change-Id: I329aba80f3003a3a5f343b8dcc3efa8502b98e24
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
---
 .../myst/variants/baseboard/devicetree.cb     | 139 ++++++++++++++++++
 1 file changed, 139 insertions(+)

diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
index 058f873cb5..2b6fa8938d 100644
--- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb
@@ -85,6 +85,145 @@ chip soc/amd/phoenix
 	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works
 	register "s0ix_enable" = "true"
 
+	register "usb_phy_custom" = "1"
+	register "usb_phy" = "{
+		.Usb2PhyPort[0] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[1] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[2] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[3] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[4] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[5] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[6] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[7] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb3PhyPort[0] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.Usb3PhyPort[1] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.Usb3PhyPort[2] = {
+			.tx_term_ctrl = 0x2,
+			.rx_term_ctrl = 0x2,
+			.tx_vboost_lvl_en = 0x0,
+			.tx_vboost_lvl = 0x5,
+		},
+		.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
+		.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
+		.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
+		.BatteryChargerEnable = 0,
+		.PhyP3CpmP4Support = 0,
+	}"
+
 	device domain 0 on
 		device ref gpp_bridge_2_1 on end # WWAN
 		device ref gpp_bridge_2_2 on # WLAN