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soc/intel/cannonlake: Rename SOC_INTEL_COMMON_CANNONLAKE_BASE 

What it really means to do is to use different FSP headers.

Change-Id: I3c75d4aac8525ab2639608fb9c1b3a9afef0e943
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-06-18 13:19:29 +02:00 committed by Patrick Georgi
parent a6a396ddb6
commit 4821a0e135
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/cannonlake/Kconfig
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@ -3,7 +3,7 @@ config SOC_INTEL_CANNONLAKE
help
Intel Cannonlake support
config SOC_INTEL_COMMON_CANNONLAKE_BASE
config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
bool
default n
select SOC_INTEL_CANNONLAKE
@ -11,7 +11,7 @@ config SOC_INTEL_COMMON_CANNONLAKE_BASE
Single Kconfig option to select common base Cannonlake support.
This Kconfig will help to select majority of CNL SoC features.
Major difference that exist today between
SOC_INTEL_COMMON_CANNONLAKE_BASE and SOC_INTEL_CANNONLAKE Kconfig
SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig
are in FSP Header Files. Hence this Kconfig might help to select
required SoC support FSP headers. Any future Intel SoC would
like to make use of CNL support might just select this Kconfig.
@ -19,21 +19,21 @@ config SOC_INTEL_COMMON_CANNONLAKE_BASE
config SOC_INTEL_COFFEELAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
help
Intel Coffeelake support
config SOC_INTEL_WHISKEYLAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
help
Intel Whiskeylake support
config SOC_INTEL_COMETLAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
select SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS
help
Intel Cometlake support

2
src/soc/intel/cannonlake/chip.h
View File

@ -111,7 +111,7 @@ struct soc_intel_cannonlake_config {
enum {
SaGv_Disabled,
SaGv_FixedLow,
#if !CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
SaGv_FixedMid,
#endif
SaGv_FixedHigh,

2
src/soc/intel/cannonlake/cpu.c
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@ -500,7 +500,7 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
* have this check, where CNL CPU die is not based on KBL CPU
* so skip this check for CNL.
*/
if (!CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE))
if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS))
return 0;
/*

2
src/soc/intel/cannonlake/romstage/fsp_params.c
View File

@ -69,7 +69,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
#if CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
#endif