From 4822630c0cdbb868e1780a17c824887c2f72a211 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Wed, 28 Aug 2019 16:51:07 +0800 Subject: [PATCH] mb/google/drallion: add memory sku id Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id. BUG=b:139397313 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a Reviewed-on: https://review.coreboot.org/c/coreboot/+/35133 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- .../drallion/variants/drallion/Makefile.inc | 2 ++ .../variants/drallion/include/variant/gpio.h | 7 +++++ .../drallion/include/variant/variant.h | 3 ++ .../drallion/variants/drallion/memory.c | 31 +++++++++++++++++++ 4 files changed, 43 insertions(+) create mode 100644 src/mainboard/google/drallion/variants/drallion/memory.c diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 0400d33189..8e070d26fb 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -20,3 +20,5 @@ bootblock-y += gpio.c ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index f7e0403e59..20cfbb8279 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -25,6 +25,13 @@ /* Recovery mode */ #define GPIO_REC_MODE GPP_E8 +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F12 +#define GPIO_MEM_CONFIG_1 GPP_F13 +#define GPIO_MEM_CONFIG_2 GPP_F14 +#define GPIO_MEM_CONFIG_3 GPP_F15 +#define GPIO_MEM_CONFIG_4 GPP_F16 + const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index d878623d59..ca54580133 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -22,4 +22,7 @@ #define VARIANT_SKU_ID_SIGNED_EC 4 #define VARIANT_SKU_NAME_SIGNED_EC "sku4" +/* Return memory SKU for the variant */ +int variant_memory_sku(void); + #endif diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c new file mode 100644 index 0000000000..e1755b4a85 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_4, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +}