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mb/system76/adl: Remove PL4 values 

System76 EC since system76/ec@99dfbeaec3 sets PL4 values through PECI
based on AC state for all boards. Remove the static PL4 values from
coreboot since they won't be used.

Ref: https://github.com/system76/ec/pull/353
Change-Id: I66bc547ef1b3419fc677fcbdd5ba5d8cc8e14189
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75333
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Crawford 2023-06-12 12:01:49 -06:00 committed by Felix Held
parent 8e8a2b496e
commit 482789b015
5 changed files with 0 additions and 9 deletions
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3
src/mainboard/system76/adl/variants/darp8/overridetree.cb
View File

@ -1,10 +1,7 @@
chip soc/intel/alderlake
# HACK: Limit PL4 to PL2 to prevent power-off when system is booted on
# battery power. This seems to only happen with the i7 units.
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 56,
.tdp_pl4 = 56, // FIXME: Set to 65
}"
# GPE configuration

1
src/mainboard/system76/adl/variants/galp6/overridetree.cb
View File

@ -2,7 +2,6 @@ chip soc/intel/alderlake
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
.tdp_pl1_override = 28,
.tdp_pl2_override = 60,
.tdp_pl4 = 90,
}"
# GPE configuration

1
src/mainboard/system76/adl/variants/lemp11/overridetree.cb
View File

@ -2,7 +2,6 @@ chip soc/intel/alderlake
register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 46,
.tdp_pl4 = 65,
}"
# GPE configuration

2
src/mainboard/system76/adl/variants/oryp10/overridetree.cb
View File

@ -1,10 +1,8 @@
chip soc/intel/alderlake
# HACK: Limit PL4 to prevent power off on battery power.
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_psyspl2 = 135,
.tdp_pl4 = 72,
}"
# Thermal

2
src/mainboard/system76/adl/variants/oryp9/overridetree.cb
View File

@ -1,10 +1,8 @@
chip soc/intel/alderlake
# HACK: Limit PL4 to prevent power off on battery power.
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_psyspl2 = 135,
.tdp_pl4 = 72,
}"
# Thermal