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src/mainboard: Fix various typos 

These typos were found through manual review and grep.

Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Jonathan Neuschäfer 2017-11-20 02:09:19 +01:00 committed by Martin Roth
parent bfd62fabc9
commit 482d16fb0a
32 changed files with 33 additions and 33 deletions
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4
src/mainboard/amd/lamar/mainboard.c
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@ -62,7 +62,7 @@ const u8 mainboard_picr_data[] = {
[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
[0x70] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
/* [80..81] Northbridge devices (indicies above C00/C01 range) */
/* [80..81] Northbridge devices (indices above C00/C01 range) */
[0x80] = 0x0C,0x1F,
};
@ -90,7 +90,7 @@ const u8 mainboard_intr_data[] = {
[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
[0x70] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
/* [80..81] Northbridge devices (indicies above C00/C01 range) */
/* [80..81] Northbridge devices (indices above C00/C01 range) */
[0x80] = 0x17,0x10,
};

2
src/mainboard/asus/kcma-d8/romstage.c
View File

@ -115,7 +115,7 @@ void activate_spd_rom(const struct mem_controller *ctrl) {
}
/* Voltages are specified by index
* Valid indicies for this platform are:
* Valid indices for this platform are:
* 0: 1.5V
* 1: 1.35V
* 2: 1.25V

2
src/mainboard/asus/kgpe-d16/romstage.c
View File

@ -131,7 +131,7 @@ void activate_spd_rom(const struct mem_controller *ctrl) {
}
/* Voltages are specified by index
* Valid indicies for this platform are:
* Valid indices for this platform are:
* 0: 1.5V
* 1: 1.35V
* 2: 1.25V

2
src/mainboard/google/chell/gpio.h
View File

@ -182,7 +182,7 @@ static const struct pad_config gpio_table[] = {
/*
* The next 4 pads are for bit banging the amplifiers. They are connected
* together with i2s0 signals. For default behavior of i2s make these
* gpio inupts.
* gpio inputs.
*/
/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),

2
src/mainboard/google/chell/romstage.c
View File

@ -32,7 +32,7 @@ void mainboard_romstage_entry(struct romstage_params *params)
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
/* Initliaze memory */
/* Initialize memory */
romstage_common(params);
}

2
src/mainboard/google/gale/mainboard.c
View File

@ -81,7 +81,7 @@ void lb_board(struct lb_header *header)
dma->range_size = _dma_coherent_size;
if (IS_ENABLED(CONFIG_CHROMEOS)) {
/* Retrieve the switch interface MAC addressses. */
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
}
}

2
src/mainboard/google/glados/gpio.h
View File

@ -185,7 +185,7 @@ static const struct pad_config gpio_table[] = {
/*
* The next 4 pads are for bit banging the amplifiers. They are connected
* together with i2s0 signals. For default behavior of i2s make these
* gpio inupts.
* gpio inputs.
*/
/* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
/* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),

2
src/mainboard/google/glados/romstage.c
View File

@ -27,7 +27,7 @@ void mainboard_romstage_entry(struct romstage_params *params)
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
/* Initliaze memory */
/* Initialize memory */
romstage_common(params);
}

2
src/mainboard/google/lars/romstage.c
View File

@ -38,7 +38,7 @@ void mainboard_romstage_entry(struct romstage_params *params)
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
/* Initliaze memory */
/* Initialize memory */
romstage_common(params);
}

2
src/mainboard/google/rambi/variants/banjo/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/candy/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/clapper/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/enguarde/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/glimmer/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/gnawty/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/heli/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# RAM_ID Vendor Vendor_PN Freq Size Total_size channel
# 0b0011 Hynix H5TC4G63AFR-PBA 1600MHZ 4Gb 2GB single-channel

2
src/mainboard/google/rambi/variants/kip/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/ninja/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/orco/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/quawks/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/rambi/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/squawks/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/sumo/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/swanky/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
# 0b001 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz

2
src/mainboard/google/rambi/variants/winky/Makefile.inc
View File

@ -15,7 +15,7 @@
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
# 0b000 - 4GiB total - 2 x 2GB - micron HTTC4G63CFR-PBA_x16_4Gb
# 0b001 - 4GiB total - 2 x Samsung_2Gib_K4B4G1646Q-HYK0

2
src/mainboard/google/reef/mainboard.c
View File

@ -72,7 +72,7 @@ uint8_t __attribute__((weak)) variant_board_sku(void)
return board_sku_num;
}
/* Set variabnt board sku to ec by sku id */
/* Set variant board sku to ec by sku id */
void __attribute__((weak)) variant_board_ec_set_skuid(void)
{
}

2
src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
View File

@ -38,7 +38,7 @@ const struct lpddr4_cfg *variant_lpddr4_config(void);
size_t variant_memory_sku(void);
/* Return board SKU. Limited to uint8_t, so it fits into 3 decimal digits */
uint8_t variant_board_sku(void);
/* Set variabnt board sku to ec by sku id */
/* Set variant board sku to ec by sku id */
void variant_board_ec_set_skuid(void);
/* Return ChromeOS gpio table and fill in number of entries. */

2
src/mainboard/google/storm/mainboard.c
View File

@ -125,7 +125,7 @@ void lb_board(struct lb_header *header)
dma->range_size = _dma_coherent_size;
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Retrieve the switch interface MAC addressses. */
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
#endif
}

2
src/mainboard/google/urara/mainboard.c
View File

@ -50,7 +50,7 @@ void lb_board(struct lb_header *header)
dma->range_size = _dma_coherent_size;
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Retrieve the switch interface MAC addressses. */
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
#endif
}

2
src/mainboard/intel/harcuvar/spd/Makefile.inc
View File

@ -18,7 +18,7 @@ romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
# Order matters for SPD sources. The following indicies
# Order matters for SPD sources. The following indices
# define the SPD data to use.
SPD_SOURCES = micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2

2
src/mainboard/intel/kunimitsu/romstage.c
View File

@ -29,7 +29,7 @@ void mainboard_romstage_entry(struct romstage_params *params)
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
/* Initliaze memory */
/* Initialize memory */
romstage_common(params);
}

2
src/mainboard/intel/strago/gpio.c
View File

@ -76,7 +76,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
Native_M1, /* 80 USB_OC0_B */
NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */
/* 81 SDMMC3_CD_B */
GPIO_NC, /* 82 spkr asummed gpio number */
GPIO_NC, /* 82 spkr assumed gpio number */
Native_M1, /* 83 SUSPWRDNACK */
SPARE_PIN,/* 84 spare pin */
Native_M1, /* 85 SDMMC3_1P8_EN */