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soc/apollolake: Add ish_enable in soc_intel_apollolake_config 

Also initialize IshEnable in Silicon Init UPD with the value from
devicetree.cb

Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I8f57a7353471cc3efa21c7011cdd0b369d25275d
Reviewed-on: https://review.coreboot.org/14894
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Hannah Williams 2016-03-28 14:45:59 -07:00 committed by Martin Roth
parent 15a53c6329
commit 483004f6d7
2 changed files with 5 additions and 0 deletions
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2
src/soc/intel/apollolake/chip.c
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@ -120,6 +120,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
silconfig->PmcBase = PMC_BAR0 + 0x1000; silconfig->PmcBase = PMC_BAR0 + 0x1000;
silconfig->P2sbBase = P2SB_BAR; silconfig->P2sbBase = P2SB_BAR;
silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
} }
struct chip_operations soc_intel_apollolake_ops = { struct chip_operations soc_intel_apollolake_ops = {

3
src/soc/intel/apollolake/chip.h
View File

@ -42,6 +42,9 @@ struct soc_intel_apollolake_config {
/* Configure serial IRQ (SERIRQ) line. */ /* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode; enum serirq_mode serirq_mode;
/* Integrated Sensor Hub */
uint8_t integrated_sensor_hub_enable;
}; };
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */ #endif /* _SOC_APOLLOLAKE_CHIP_H_ */