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AGESA: Only fam14 sets Ontario APU IDs 

Change-Id: I3d249a1234599e3820e4ad9b852bbb03a89dd49a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7810
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2014-12-14 09:26:04 +02:00 committed by Stefan Reinauer
parent 569bd3ff60
commit 483bed33a9
4 changed files with 4 additions and 14 deletions
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3
src/northbridge/amd/agesa/agesawrapper.h
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@ -24,9 +24,6 @@
#include "Porting.h"
#include "AGESA.h"
/* Define AMD Ontario APPU SSID/SVID */
#define AMD_APU_SVID 0x1022
#define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum {

8
src/northbridge/amd/agesa/family12/agesawrapper.c
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@ -186,14 +186,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
MsrReg = MsrReg | 0x0000400000000000ull;
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
//- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
//- PciData = 0x01308002;
//- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
//- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
//- PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
//- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Enable Non-Post Memory in CPU */
PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);

4
src/northbridge/amd/agesa/family14/agesawrapper.c
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@ -36,6 +36,10 @@
#define MMCONF_ENABLE 1
/* Define AMD Ontario APPU SSID/SVID */
#define AMD_APU_SVID 0x1022
#define AMD_APU_SSID 0x1234
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;

3
src/northbridge/amd/pi/agesawrapper.h
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@ -24,9 +24,6 @@
#include "Porting.h"
#include "AGESA.h"
/* Define AMD APU and SoC SSID/SVID */
#define AMD_APU_SVID 0x1022
#define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum {