AGESA: Only fam14 sets Ontario APU IDs
Change-Id: I3d249a1234599e3820e4ad9b852bbb03a89dd49a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7810 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -24,9 +24,6 @@
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#include "Porting.h"
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#include "Porting.h"
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#include "AGESA.h"
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#include "AGESA.h"
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/* Define AMD Ontario APPU SSID/SVID */
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#define AMD_APU_SVID 0x1022
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#define AMD_APU_SSID 0x1234
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#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
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#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
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enum {
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enum {
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@ -186,14 +186,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(VOID)
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MsrReg = MsrReg | 0x0000400000000000ull;
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MsrReg = MsrReg | 0x0000400000000000ull;
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LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
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LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
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/* Set Ontario Link Data */
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//- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
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//- PciData = 0x01308002;
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//- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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//- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
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//- PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
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//- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Enable Non-Post Memory in CPU */
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/* Enable Non-Post Memory in CPU */
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PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
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PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x3FF80);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
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@ -36,6 +36,10 @@
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#define MMCONF_ENABLE 1
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#define MMCONF_ENABLE 1
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/* Define AMD Ontario APPU SSID/SVID */
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#define AMD_APU_SVID 0x1022
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#define AMD_APU_SSID 0x1234
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/* ACPI table pointers returned by AmdInitLate */
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/* ACPI table pointers returned by AmdInitLate */
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VOID *DmiTable = NULL;
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VOID *DmiTable = NULL;
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VOID *AcpiPstate = NULL;
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VOID *AcpiPstate = NULL;
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@ -24,9 +24,6 @@
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#include "Porting.h"
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#include "Porting.h"
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#include "AGESA.h"
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#include "AGESA.h"
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/* Define AMD APU and SoC SSID/SVID */
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#define AMD_APU_SVID 0x1022
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#define AMD_APU_SSID 0x1234
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#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
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#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
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enum {
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enum {
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