sandybridge: Store MRC cache in CBFS
Location is hard-coded right now, which isn't optimal. It must be chip erase block aligned, which might fail on some flash chips (it's 64k aligned which should work for most cases). Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3497 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
parent
44c392f8c2
commit
483ff82539
|
@ -43,4 +43,14 @@ mrc.bin-position := 0xfffe0000
|
|||
endif
|
||||
mrc.bin-type := 0xab
|
||||
|
||||
$(obj)/mrc.cache:
|
||||
dd if=/dev/zero count=1 \
|
||||
bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
|
||||
tr '\000' '\377' > $@
|
||||
|
||||
cbfs-files-$(CONFIG_HAVE_MRC) += mrc.cache
|
||||
mrc.cache-file := $(obj)/mrc.cache
|
||||
mrc.cache-position := 0xfff80000
|
||||
mrc.cache-type := 0xac
|
||||
|
||||
$(obj)/northbridge/intel/sandybridge/acpi.ramstage.o : $(obj)/build.h
|
||||
|
|
|
@ -71,8 +71,8 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
|
|||
region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr);
|
||||
#else
|
||||
region_size = CONFIG_MRC_CACHE_SIZE;
|
||||
*mrc_region_ptr = (struct mrc_data_container *)
|
||||
(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION);
|
||||
*mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
|
||||
"mrc.cache", 0xac);
|
||||
#endif
|
||||
|
||||
return region_size;
|
||||
|
|
Loading…
Reference in New Issue