X201: Fix SMI bindings.
Doesn't have a visible effect currently but it's better if those bindings are correct. Change-Id: I0f1a468e59429b14db139cc48e1e68c0e1841300 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4645 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -18,6 +18,7 @@
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##
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smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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romstage-y += dock.c
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ramstage-y += dock.c
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ramstage-y += gma.c
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@ -24,6 +24,9 @@
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#include <cpu/x86/smm.h>
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#include "southbridge/intel/ibexpeak/nvs.h"
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#include "southbridge/intel/ibexpeak/pch.h"
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#include "southbridge/intel/ibexpeak/me.h"
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <cpu/intel/model_2065x/model_2065x.h>
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#include <ec/acpi/ec.h>
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#include <pc80/mc146818rtc.h>
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#include <ec/lenovo/h8/h8.h>
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@ -134,10 +137,12 @@ static void mainboard_smi_handle_ec_sci(void)
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void mainboard_smi_gpi(u32 gpi_sts)
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{
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if (gpi_sts & (1 << 12))
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if (gpi_sts & (1 << 1))
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mainboard_smi_handle_ec_sci();
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}
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static int mainboard_finalized = 0;
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int mainboard_smi_apmc(u8 data)
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{
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u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
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@ -150,6 +155,20 @@ int mainboard_smi_apmc(u8 data)
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return 0;
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switch (data) {
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case APM_CNT_FINALIZE:
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printk(BIOS_DEBUG, "APMC: FINALIZE\n");
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if (mainboard_finalized) {
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printk(BIOS_DEBUG, "APMC#: Already finalized\n");
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return 0;
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}
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intel_me_finalize_smm();
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intel_pch_finalize_smm();
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intel_sandybridge_finalize_smm();
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intel_model_2065x_finalize_smm();
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mainboard_finalized = 1;
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break;
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case APM_CNT_ACPI_ENABLE:
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/* use 0x1600/0x1604 to prevent races with userspace */
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ec_set_ports(0x1604, 0x1600);
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