From 487c1a24f59c19539b6039c54176e87864ab91b8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 31 Jan 2021 08:23:00 +0100 Subject: [PATCH] nb/intel/i945/bootblock.c: include Also replace 'reg' with 'reg32'. Change-Id: I2aa8862de0f7629386ef09acbb0606056cc3697c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/49537 Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/northbridge/intel/i945/bootblock.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index f4b46282ca..edb9a8d4d0 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include -#include #include + #include "i945.h" static uint32_t encode_pciexbar_length(void) @@ -27,6 +28,6 @@ void bootblock_early_northbridge_init(void) * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); }