From 487cd399dfa6a2601c540ff443c994f2d077aa91 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 10 Feb 2023 21:10:06 +0530 Subject: [PATCH] mb/google/rex: Set `SkipExtGfxScan` FSP-M UPD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch overrides `SkipExtGfxScan` UPD as the Rex device is equipped with an on-board graphics device hence, skip scanning external GFX devices. BUG=b:228002764 TEST=Able to save ~1ms+ boot time on google/rex. FSP FPDT Data is showing the timestamp between those function calls. Without this patch: [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22 [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131 With this patch: `CheckOffboardPcieVga` is not getting called. Signed-off-by: Subrata Banik Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948 Tested-by: build bot (Jenkins) Reviewed-by: Dinesh Gehlot Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index a3225ca111..d31cafc83a 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -20,6 +20,9 @@ chip soc/intel/meteorlake # Enable CNVi BT register "cnvi_bt_core" = "true" + # Set on-board graphics as primary display + register "skip_ext_gfx_scan" = "1" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, [PchSerialIoIndexUART1] = PchSerialIoDisabled,