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amdfwtool: Add a macro to set explicitly second gen for old SOCs 

It is more reasonable than getting the value from memset.

For the reserved bits, keep them as they were for old SOCs.

Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Zheng Bao 2022-04-03 12:50:07 +08:00 committed by Felix Held
parent ac43324211
commit 487d04540b
2 changed files with 6 additions and 1 deletions
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6
util/amdfwtool/amdfwtool.c
View File

@ -1383,6 +1383,8 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig,
} }
switch (soc_id) { switch (soc_id) {
case PLATFORM_STONEYRIDGE: case PLATFORM_STONEYRIDGE:
amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
amd_romsig->efs_gen.reserved = ~0;
amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode;
amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed;
break; break;
@ -1390,6 +1392,8 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig,
case PLATFORM_PICASSO: case PLATFORM_PICASSO:
/* amd_romsig->efs_gen introduced after RAVEN/PICASSO. /* amd_romsig->efs_gen introduced after RAVEN/PICASSO.
* Leave as 0xffffffff for first gen */ * Leave as 0xffffffff for first gen */
amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
amd_romsig->efs_gen.reserved = ~0;
amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode;
amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed;
switch (efs_spi_micron_flag) { switch (efs_spi_micron_flag) {
@ -1410,6 +1414,7 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig,
case PLATFORM_MENDOCINO: case PLATFORM_MENDOCINO:
case PLATFORM_SABRINA: case PLATFORM_SABRINA:
amd_romsig->efs_gen.gen = EFS_SECOND_GEN; amd_romsig->efs_gen.gen = EFS_SECOND_GEN;
amd_romsig->efs_gen.reserved = 0;
amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode;
amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed;
switch (efs_spi_micron_flag) { switch (efs_spi_micron_flag) {
@ -1803,7 +1808,6 @@ int main(int argc, char **argv)
amd_romsig->imc_entry = 0; amd_romsig->imc_entry = 0;
amd_romsig->gec_entry = 0; amd_romsig->gec_entry = 0;
amd_romsig->xhci_entry = 0; amd_romsig->xhci_entry = 0;
amd_romsig->efs_gen.reserved = 0;
if (soc_id != PLATFORM_UNKNOWN) { if (soc_id != PLATFORM_UNKNOWN) {
retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode,

1
util/amdfwtool/amdfwtool.h
View File

@ -88,6 +88,7 @@ struct second_gen_efs { /* todo: expand for Server products */
} __attribute__((packed)); } __attribute__((packed));
#define EFS_SECOND_GEN 0 #define EFS_SECOND_GEN 0
#define EFS_BEFORE_SECOND_GEN 1
typedef struct _embedded_firmware { typedef struct _embedded_firmware {
uint32_t signature; /* 0x55aa55aa */ uint32_t signature; /* 0x55aa55aa */