From 489300358114fe6f9f43aaf02d72c64bf8bc54aa Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Thu, 10 Feb 2022 16:19:03 +0800 Subject: [PATCH] mb/google/brya/var/agah: Update Aux settings Agah port 0 does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/agah/overridetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 3856df2039..f890582ee5 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -1,5 +1,4 @@ chip soc/intel/alderlake - register "SaGv" = "SaGv_Enabled" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -31,6 +30,10 @@ chip soc/intel/alderlake }, }" + register "SaGv" = "SaGv_Enabled" + register "TcssAuxOri" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN register "usb2_ports[4]" = "USB2_PORT_EMPTY" #