src/vendorcode/intel: Update Comet Lake FSP headers as per FSP v1394
"EnforceEDebugMode" UPD added in FSP_S_TEST_CONFIG Change-Id: I1583d8583db20b29505e5a7ae4084013334c87c2 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35852 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -3621,7 +3621,17 @@ typedef struct {
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**/
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**/
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UINT32 SdCardRxCmdDataDelay2RegValue;
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UINT32 SdCardRxCmdDataDelay2RegValue;
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/** Offset 0x0ABC
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/** Offset 0x0ABC - Enforce Enhanced Debug Mode
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Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable
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$EN_DIS
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**/
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UINT8 EnforceEDebugMode;
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/** Offset 0x0ABD
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**/
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UINT8 UnusedUpdSpace31[7];
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/** Offset 0x0AC4
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**/
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**/
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UINT8 ReservedFspsTestUpd[12];
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UINT8 ReservedFspsTestUpd[12];
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} FSP_S_TEST_CONFIG;
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} FSP_S_TEST_CONFIG;
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@ -3642,11 +3652,11 @@ typedef struct {
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**/
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**/
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FSP_S_TEST_CONFIG FspsTestConfig;
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FSP_S_TEST_CONFIG FspsTestConfig;
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/** Offset 0x0AC8
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/** Offset 0x0AD0
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**/
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**/
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UINT8 UnusedUpdSpace31[6];
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UINT8 UnusedUpdSpace32[6];
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/** Offset 0x0ACE
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/** Offset 0x0AD6
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**/
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**/
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UINT16 UpdTerminator;
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UINT16 UpdTerminator;
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} FSPS_UPD;
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} FSPS_UPD;
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