src/vendorcode/intel: Update Comet Lake FSP headers as per FSP v1394
"EnforceEDebugMode" UPD added in FSP_S_TEST_CONFIG Change-Id: I1583d8583db20b29505e5a7ae4084013334c87c2 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35852 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -37,49 +37,49 @@ are permitted provided that the following conditions are met:
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#pragma pack(1)
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#pragma pack(1)
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///
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///
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/// Azalia Header structure
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/// Azalia Header structure
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///
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///
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typedef struct {
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typedef struct {
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UINT16 VendorId; ///< Codec Vendor ID
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UINT16 VendorId; ///< Codec Vendor ID
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UINT16 DeviceId; ///< Codec Device ID
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UINT16 DeviceId; ///< Codec Device ID
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UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
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UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
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UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
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UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
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UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
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UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
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UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
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UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
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} AZALIA_HEADER;
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} AZALIA_HEADER;
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///
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///
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/// Audio Azalia Verb Table structure
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/// Audio Azalia Verb Table structure
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///
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///
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typedef struct {
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typedef struct {
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AZALIA_HEADER Header; ///< AZALIA PCH header
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AZALIA_HEADER Header; ///< AZALIA PCH header
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UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
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UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
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} AUDIO_AZALIA_VERB_TABLE;
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} AUDIO_AZALIA_VERB_TABLE;
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///
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///
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/// Refer to the definition of PCH_INT_PIN
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/// Refer to the definition of PCH_INT_PIN
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///
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///
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typedef enum {
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typedef enum {
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SiPchNoInt, ///< No Interrupt Pin
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SiPchNoInt, ///< No Interrupt Pin
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SiPchIntA,
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SiPchIntA,
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SiPchIntB,
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SiPchIntB,
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SiPchIntC,
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SiPchIntC,
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SiPchIntD
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SiPchIntD
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} SI_PCH_INT_PIN;
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} SI_PCH_INT_PIN;
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///
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///
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/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
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/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
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///
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///
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typedef struct {
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typedef struct {
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UINT8 Device; ///< Device number
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UINT8 Device; ///< Device number
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UINT8 Function; ///< Device function
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UINT8 Function; ///< Device function
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UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
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UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
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UINT8 Irq; ///< IRQ to be set for device.
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UINT8 Irq; ///< IRQ to be set for device.
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} SI_PCH_DEVICE_INTERRUPT_CONFIG;
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} SI_PCH_DEVICE_INTERRUPT_CONFIG;
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#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
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#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
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/** Fsp S Configuration
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/** Fsp S Configuration
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**/
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**/
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@ -3621,7 +3621,17 @@ typedef struct {
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**/
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**/
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UINT32 SdCardRxCmdDataDelay2RegValue;
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UINT32 SdCardRxCmdDataDelay2RegValue;
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/** Offset 0x0ABC
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/** Offset 0x0ABC - Enforce Enhanced Debug Mode
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Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable
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$EN_DIS
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**/
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UINT8 EnforceEDebugMode;
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/** Offset 0x0ABD
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**/
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UINT8 UnusedUpdSpace31[7];
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/** Offset 0x0AC4
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**/
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**/
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UINT8 ReservedFspsTestUpd[12];
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UINT8 ReservedFspsTestUpd[12];
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} FSP_S_TEST_CONFIG;
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} FSP_S_TEST_CONFIG;
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@ -3642,11 +3652,11 @@ typedef struct {
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**/
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**/
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FSP_S_TEST_CONFIG FspsTestConfig;
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FSP_S_TEST_CONFIG FspsTestConfig;
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/** Offset 0x0AC8
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/** Offset 0x0AD0
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**/
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**/
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UINT8 UnusedUpdSpace31[6];
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UINT8 UnusedUpdSpace32[6];
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/** Offset 0x0ACE
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/** Offset 0x0AD6
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**/
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**/
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UINT16 UpdTerminator;
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UINT16 UpdTerminator;
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} FSPS_UPD;
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} FSPS_UPD;
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