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mb/google/hatch: Enable LPIT inclusion in DSDT 

Include the lpit.asl file in Hatch's DSDT definition.

BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.

Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This commit is contained in:
Tim Wawrzynczak 2019-07-09 13:30:30 -06:00 committed by Martin Roth
parent 145748bf25
commit 489c722dcc
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/hatch/dsdt.asl
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@ -51,6 +51,9 @@ DefinitionBlock(
/* Chipset specific sleep states */ /* Chipset specific sleep states */
#include <soc/intel/cannonlake/acpi/sleepstates.asl> #include <soc/intel/cannonlake/acpi/sleepstates.asl>
/* Low power idle table */
#include <soc/intel/cannonlake/acpi/lpit.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)
{ {