From 48a6c018bcb8a182c4934d2788567e512d490f96 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 8 Jul 2020 09:22:13 +0200 Subject: [PATCH] src: Remove redundant use of ACPI offset(0) IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held Reviewed-by: Marshall Dawson Reviewed-by: Jason Glenesk Tested-by: build bot (Jenkins) --- src/ec/compal/ene932/acpi/ec.asl | 3 +-- src/ec/google/chromeec/acpi/ec.asl | 1 - src/ec/google/chromeec/acpi/emem.asl | 1 - src/ec/quanta/it8518/acpi/ec.asl | 2 +- src/ec/roda/it8518/acpi/ec.asl | 1 - src/mainboard/facebook/monolith/acpi/ec.asl | 1 - src/mainboard/lenovo/s230u/acpi/ec.asl | 1 - src/mainboard/lippert/frontrunner-af/dsdt.asl | 3 +-- src/soc/amd/picasso/acpi/globalnvs.asl | 1 - src/soc/amd/stoneyridge/acpi/globalnvs.asl | 1 - src/soc/intel/apollolake/acpi/globalnvs.asl | 1 - src/soc/intel/baytrail/acpi/globalnvs.asl | 1 - src/soc/intel/broadwell/pch/acpi/globalnvs.asl | 1 - src/soc/intel/broadwell/pch/acpi/xhci.asl | 1 - src/soc/intel/cannonlake/acpi/scs.asl | 3 +-- src/soc/intel/denverton_ns/acpi/globalnvs.asl | 1 - src/soc/intel/skylake/acpi/globalnvs.asl | 1 - src/soc/intel/skylake/acpi/xhci.asl | 1 - src/southbridge/amd/cimx/sb800/acpi/fch.asl | 3 +-- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 1 - src/southbridge/intel/bd82x6x/acpi/pch.asl | 3 +-- src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 1 - src/southbridge/intel/i82801ix/acpi/ich9.asl | 3 +-- src/southbridge/intel/i82801jx/acpi/globalnvs.asl | 1 - src/southbridge/intel/i82801jx/acpi/ich10.asl | 2 +- src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 1 - src/southbridge/intel/lynxpoint/acpi/xhci.asl | 1 - src/superio/fintek/f81803a/acpi/superio.asl | 5 ++--- .../f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl | 2 -- .../f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl | 2 -- 30 files changed, 10 insertions(+), 40 deletions(-) diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index 6b0997e37d..c4fa3a38d3 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -16,8 +16,7 @@ Device (EC0) Field (ERAM, ByteAcc, Lock, Preserve) { // EC Name Space Configuration - Offset(0x00), - , 1, // Reserved ; 00h.0 + , 1, // Reserved ; 00h.0 LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 , 6, // Reserved ; 00h.2 ~ 00h.6 HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index ce2455f30b..218d08b091 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -31,7 +31,6 @@ Device (EC0) OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset (0x00), RAMV, 8, // EC RAM Version TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl index 77a6f71139..2a556edc68 100644 --- a/src/ec/google/chromeec/acpi/emem.asl +++ b/src/ec/google/chromeec/acpi/emem.asl @@ -4,7 +4,6 @@ * EMEM data may be accessed through port 62/66 or through LPC at 900h. */ -Offset (0x00), TIN0, 8, // Temperature 0 TIN1, 8, // Temperature 1 TIN2, 8, // Temperature 2 diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index a3598bef07..093593cfce 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -16,7 +16,7 @@ Device (EC0) OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0] + // [Configuration Space 0] , 1, // Reserved bit[0] ENGA, 1, // Enable Global attention ENHY, 1, // Enable Hotkey function diff --git a/src/ec/roda/it8518/acpi/ec.asl b/src/ec/roda/it8518/acpi/ec.asl index d500084cf2..de121c6226 100644 --- a/src/ec/roda/it8518/acpi/ec.asl +++ b/src/ec/roda/it8518/acpi/ec.asl @@ -14,7 +14,6 @@ Device (EC0) OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0x0] Offset(0x02), // [Configuration Space 0x2] B0ST, 16, // Battery 0 State B0FC, 16, // Battery 0 Last Full Charge Capacity diff --git a/src/mainboard/facebook/monolith/acpi/ec.asl b/src/mainboard/facebook/monolith/acpi/ec.asl index e729e0140b..d9a072952e 100644 --- a/src/mainboard/facebook/monolith/acpi/ec.asl +++ b/src/mainboard/facebook/monolith/acpi/ec.asl @@ -29,7 +29,6 @@ Device (EC0) OperationRegion (ERAM, EmbeddedControl, 0x00, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset (0x00), CPUT, 8, } diff --git a/src/mainboard/lenovo/s230u/acpi/ec.asl b/src/mainboard/lenovo/s230u/acpi/ec.asl index 888feac2cc..20a9096395 100644 --- a/src/mainboard/lenovo/s230u/acpi/ec.asl +++ b/src/mainboard/lenovo/s230u/acpi/ec.asl @@ -12,7 +12,6 @@ Device (EC0) OperationRegion (ERAM, SystemMemory, (CONFIG_EC_BASE_ADDRESS + 0x100), 0x100) Field (ERAM, ByteAcc, Lock, Preserve) { - Offset(0x00), , 1, , 1, HKFA, 1, // FN lock (Hotkey / FN row toggle) diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index ffae0d932f..e0804ed159 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -134,8 +134,7 @@ DefinitionBlock ( PIOD, 0x00000008, } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, + , 1, /* MiscControl */ T1EE, 1, T2EE, 1, Offset(0x01), /* MiscStatus */ diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 6790a5f4a6..709649211d 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count LIDS, 8, // 0x01 - LID State PWRS, 8, // 0x02 - AC Power State diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 0acc408f0f..8bfc7b2b80 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -12,7 +12,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count LIDS, 8, // 0x01 - LID State PWRS, 8, // 0x02 - AC Power State diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 82f41b3c64..8b03713f05 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -12,7 +12,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), PCNT, 8, // 0x00 - Processor Count PPCM, 8, // 0x01 - Max PPC State LIDS, 8, // 0x02 - LID State diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index c472d06ea1..ad77a832a8 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -17,7 +17,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, /* 0x00 - Operating System */ SMIF, 8, /* 0x02 - SMI function */ PRM0, 8, /* 0x03 - SMI function parameter */ diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index 06ca564548..7ee7e1396e 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -16,7 +16,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/broadwell/pch/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl index 4bdd3103f1..0656a6cf2a 100644 --- a/src/soc/intel/broadwell/pch/acpi/xhci.asl +++ b/src/soc/intel/broadwell/pch/acpi/xhci.asl @@ -12,7 +12,6 @@ Device (XHCI) OperationRegion (XPRT, PCI_Config, 0, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, Offset (0x10), , 16, diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 8e1de1e0e1..462e65a086 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -23,8 +23,7 @@ Scope (\_SB.PCI0) { OperationRegion(SCSR, PCI_Config, 0x00, 0x100) Field(SCSR, WordAcc, NoLock, Preserve) { - Offset (0x0), /* PCI VID DID */ - VDID, 32, + VDID, 32, /* PCI VID DID */ Offset (0x84), /* PMECTRLSTATUS */ PMCR, 16, Offset (0xA2), /* PG_CONFIG */ diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index 7ce6c7a913..4725cec5f8 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -16,7 +16,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index abcde9421b..bc99698e1c 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -17,7 +17,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 2f5d8b2200..978c7e3964 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -83,7 +83,6 @@ Device (XHCI) OperationRegion (XPRT, PCI_Config, 0x00, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, /* VENDORID */ Offset (0x10), , 16, diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 0c0150de95..0986b69070 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -213,8 +213,7 @@ Scope(\){ PIOD, 0x00000008, } IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0x00), /* MiscControl */ - , 1, + , 1, /* MiscControl */ T1EE, 1, T2EE, 1, Offset(0x01), /* MiscStatus */ diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index f9944720a8..46096cc66b 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 4f08a64e8a..4a033abfb1 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -63,8 +63,7 @@ Scope(\) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select - GU00, 8, + GU00, 8, // GPIO Use Select GU01, 8, GU02, 8, GU03, 8, diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 0a0f25511b..5c9e26ea27 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 25a756e87f..f720505c08 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -32,8 +32,7 @@ Scope(\) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select - GU00, 8, + GU00, 8, // GPIO Use Select GU01, 8, GU02, 8, GU03, 8, diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 0a0f25511b..5c9e26ea27 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x100) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index e62f8a1a80..d6136af14f 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -33,7 +33,7 @@ Scope(\) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) Field(GPIO, ByteAcc, NoLock, Preserve) { - Offset(0x00), // GPIO Use Select + // GPIO Use Select GU00, 8, GU01, 8, GU02, 8, diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ccf9b087b3..482718a4ea 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -16,7 +16,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PRM0, 8, // 0x03 - SMI function parameter diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index fbeb56200a..a65b1f6202 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -12,7 +12,6 @@ Device (XHCI) OperationRegion (XPRT, PCI_Config, 0, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { - Offset (0x0), DVID, 16, Offset (0x10), , 16, diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl index 4e2c525856..87574a8b5a 100644 --- a/src/superio/fintek/f81803a/acpi/superio.asl +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -234,9 +234,8 @@ Device(SUPERIO_DEV) { OperationRegion(APCx, SystemIO, APC5, 0x01) Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ { - Offset(0x00), /*Control Reg 5 */ - , 7, - PSIN, 1 /* PSIN_FLAG */ + , 7, /*Control Reg 5 */ + PSIN, 1 /* PSIN_FLAG */ } /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl index 463093c6b1..5d545b189b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl @@ -142,7 +142,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } return (varPciReg32) @@ -160,7 +159,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } Store (Arg2, varPciReg32) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl index 9dba662995..342c646db5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl @@ -55,7 +55,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } return (varPciReg32) @@ -73,7 +72,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } Store (Arg2, varPciReg32)