util/inteltool: Add Skylake Desktop Northbridge
Add the 8086:191f North/Host Bridge to the list of definitions. Adding the definiton makes the Northbridge get recognized by inteltool. It is found in the Intel i5-6600K CPU: https://ark.intel.com/products/88191/Intel-Core-i5-6600K-Processor-6M-Cache-up-to-3_90-GHz Change-Id: Id746d1e8b3bb90b3b68a2f6c372890671dd61b5f Signed-off-by: Christoph Pomaska <cp_public@gmx.de> Reviewed-on: https://review.coreboot.org/23055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -115,6 +115,8 @@ static const struct {
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"6th generation (Skylake-H family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST,
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"6th generation (Skylake-S/H family) Core Processor (Workstation)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D,
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"6th generation (Skylake-S family) Core Processor (Desktop)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
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/* Southbridges (LPC controllers) */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
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@ -223,7 +223,8 @@ static inline uint32_t inl(unsigned port)
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
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#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
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#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918
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#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */
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#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */
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/* Intel GPUs */
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#define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982
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@ -219,6 +219,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
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mchbar_phys = pci_read_long(nb, 0x48);
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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@ -265,6 +265,7 @@ int print_epbar(struct pci_dev *nb)
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case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
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break;
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@ -385,6 +386,7 @@ int print_dmibar(struct pci_dev *nb)
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break;
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
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dmi_registers = skylake_dmi_registers;
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size = ARRAY_SIZE(skylake_dmi_registers);
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dmibar_phys = pci_read_long(nb, 0x68);
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@ -489,6 +491,7 @@ int print_pciexbar(struct pci_dev *nb)
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case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
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pciexbar_reg = pci_read_long(nb, 0x60);
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pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
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break;
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