drivers/analogix/anx7625: prevent video clock jitter on IVO panels
The MIPI source video data has a large variation (e.g. 59Hz ~ 61Hz), anx7625 defines K ratio for matching MIPI input video clock and DP output video clock. A bigger k value can match a bigger video data variation. IVO panel has smaller variation than DP CTS spec, so decrease k value to 0x3b. BUG=b:194659777 BRANCH=none TEST=Display is normal on Asurada Change-Id: If3a09811999babda45e9a9a559dd447920109204 Signed-off-by: Xin Ji <xji@analogixsemi.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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@ -381,7 +381,7 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
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ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_PLL_N_NUM_7_0,
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(n & 0xff));
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/* diff */
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ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, 0x3d);
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ret |= anx7625_reg_write(bus, RX_P1_ADDR, MIPI_DIGITAL_ADJ_1, dt->k_val);
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ret |= anx7625_odfc_config(bus, post_divider - 1);
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@ -804,6 +804,20 @@ static void anx7625_parse_edid(const struct edid *edid,
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dt->vback_porch = (edid->mode.vbl - edid->mode.vso -
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edid->mode.vspw - edid->mode.vborder);
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/*
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* The k_val is a ratio to match MIPI input and DP output video clocks.
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* Most panels can follow the default value (0x3d).
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* IVO panels have smaller variation than DP CTS spec and need smaller
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* k_val (0x3b).
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*/
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if (!strncmp(edid->manufacturer_name, "IVO", 3)) {
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dt->k_val = 0x3b;
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ANXINFO("detected IVO panel, use k value 0x3b\n");
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} else {
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dt->k_val = 0x3d;
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ANXINFO("set default k value to 0x3d for panel\n");
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}
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ANXINFO("pixelclock(%d).\n"
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" hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n"
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" vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n",
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@ -350,6 +350,7 @@ struct display_timing {
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unsigned int vfront_porch;
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unsigned int vback_porch;
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unsigned int vsync_len;
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unsigned int k_val;
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};
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int anx7625_dp_start(uint8_t bus, const struct edid *edid);
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