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mb/google/zork: Disable SATA device for all Zork platforms to save power 

SATA is currently turned on in the Dalboz and Trembyle base board
variant devicetrees, even though no Google/Zork device uses SATA; for
mass storage they either use eMMC or NVME PCIe SSDs. This patch disables
both the SATA PCIe device and the bus where it was the only enabled
device on. The next patch in this patch train sets a new FSP-M UPD
setting

BUG=b:162302027

Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt Papageorge 2020-07-30 15:32:34 -05:00 committed by Furquan Shaikh
parent b87effe1dd
commit 48b2b2b8c1
2 changed files with 4 additions and 4 deletions
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4
src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
View File

@ -286,8 +286,8 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
device pci 8.2 on # Internal GPP Bridge 0 to Bus B
device pci 0.0 on end # AHCI
device pci 8.2 off # Internal GPP Bridge 0 to Bus B
device pci 0.0 off end # AHCI
end
device pci 14.0 on end # SM
device pci 14.3 on # - D14F3 bridge

4
src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
View File

@ -315,8 +315,8 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
device pci 8.2 on # Internal GPP Bridge 0 to Bus B
device pci 0.0 on end # AHCI
device pci 8.2 off # Internal GPP Bridge 0 to Bus B
device pci 0.0 off end # AHCI
end
device pci 14.0 on end # SM
device pci 14.3 on # - D14F3 bridge