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src: Too many terminators ';;' at end of stmts, stop Skynet 

Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Edward O'Callaghan 2014-11-09 12:06:19 +11:00 committed by Patrick Georgi
parent 27cf24727c
commit 48b6b97eb4
7 changed files with 7 additions and 7 deletions
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2
src/mainboard/google/rambi/mainboard_smi.c
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@ -139,7 +139,7 @@ int mainboard_smi_apmc(uint8_t apmc)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;

2
src/soc/intel/baytrail/refcode.c
View File

@ -90,7 +90,7 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
c->magic = RAMSTAGE_CACHE_MAGIC;
c->entry_point = (uint32_t)rsl->entry;
c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry);
c->size = cbmem_entry_size(rsl->cbmem_entry);;
c->size = cbmem_entry_size(rsl->cbmem_entry);
printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
&c->program[0], c->size);

2
src/soc/intel/broadwell/refcode.c
View File

@ -95,7 +95,7 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
c->magic = RAMSTAGE_CACHE_MAGIC;
c->entry_point = (uint32_t)rsl->entry;
c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry);
c->size = cbmem_entry_size(rsl->cbmem_entry);;
c->size = cbmem_entry_size(rsl->cbmem_entry);
printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
&c->program[0], c->size);

2
src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c
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@ -837,7 +837,7 @@ LibAmdPciWrite (
LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
}
//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
} else {
// Setup the MMIO address

2
src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
View File

@ -842,7 +842,7 @@ LibAmdPciWrite (
LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
}
//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
} else {
// Setup the MMIO address

2
src/vendorcode/amd/cimx/sb800/DISPATCHER.c
View File

@ -159,7 +159,7 @@ AmdSbDispatcher (
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
sbECfancontrolservice((AMDSBCFG*)pConfig);;
sbECfancontrolservice((AMDSBCFG*)pConfig);
}
#endif
return Status;

2
src/vendorcode/amd/pi/00730F01/Lib/amdlib.c
View File

@ -865,7 +865,7 @@ LibAmdPciWrite (
LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
}
//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
} else {
// Setup the MMIO address