src: Too many terminators ';;' at end of stmts, stop Skynet
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -139,7 +139,7 @@ int mainboard_smi_apmc(uint8_t apmc)
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google_chromeec_set_sci_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0);
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google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
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google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
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break;
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}
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return 0;
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@ -90,7 +90,7 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
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c->magic = RAMSTAGE_CACHE_MAGIC;
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c->entry_point = (uint32_t)rsl->entry;
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c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry);
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c->size = cbmem_entry_size(rsl->cbmem_entry);;
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c->size = cbmem_entry_size(rsl->cbmem_entry);
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printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
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&c->program[0], c->size);
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@ -95,7 +95,7 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
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c->magic = RAMSTAGE_CACHE_MAGIC;
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c->entry_point = (uint32_t)rsl->entry;
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c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry);
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c->size = cbmem_entry_size(rsl->cbmem_entry);;
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c->size = cbmem_entry_size(rsl->cbmem_entry);
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printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
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&c->program[0], c->size);
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@ -837,7 +837,7 @@ LibAmdPciWrite (
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LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
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}
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//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
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//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
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//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
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//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
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} else {
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// Setup the MMIO address
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@ -842,7 +842,7 @@ LibAmdPciWrite (
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LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
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}
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//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
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//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
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//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
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//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
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} else {
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// Setup the MMIO address
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@ -159,7 +159,7 @@ AmdSbDispatcher (
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}
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if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
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sbECfancontrolservice((AMDSBCFG*)pConfig);;
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sbECfancontrolservice((AMDSBCFG*)pConfig);
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}
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#endif
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return Status;
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@ -865,7 +865,7 @@ LibAmdPciWrite (
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LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
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}
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//IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
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//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);;
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//printk(BIOS_DEBUG, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
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//printk(BIOS_DEBUG, "LibAmdPciWrite\n");
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} else {
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// Setup the MMIO address
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