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soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT 

Provide the PM1_TMR information in the FADT even if PmTimerDisabled is
set because PM timer emulation is enabled via MSR 121h so the timer will
still work and can be used by things like Tianocore and Windows.

Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT).

Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Meera Ravindranath 2019-12-12 10:37:49 +05:30 committed by Patrick Georgi
parent 408d1dac9e
commit 48c7870e52
3 changed files with 24 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/soc/intel/cannonlake/acpi.c
View File

@ -179,16 +179,14 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
const struct soc_intel_cannonlake_config *config;
config = config_of_soc();
if (!config->PmTimerDisabled) {
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->pm_tmr_len = 4;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
}
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->pm_tmr_len = 4;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;

18
src/soc/intel/icelake/acpi.c
View File

@ -172,16 +172,14 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
config_t *config = config_of_soc();
if (!config->PmTimerDisabled) {
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->pm_tmr_len = 4;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
}
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->pm_tmr_len = 4;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;

18
src/soc/intel/tigerlake/acpi.c
View File

@ -171,16 +171,14 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
config_t *config = config_of_soc();
if (!config->PmTimerDisabled) {
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->pm_tmr_len = 4;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
}
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->pm_tmr_len = 4;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = 0;
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;