GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/kahlee: Fix IRQ routing 

ACPI interrupt routing file routing.asl is not reflecting AGESA settings to
the NB Interrupt Routing Registers. The AGESA settings are:
Device  self    INTA    INTB    INTC    INTD
GPP 0	23	0	1	2	3
GPP 1	24	8	9	10	11
GPP 2	25	16	17	18	19
GPP 3	26	24	25	26	27
GPP 4	23	3	0	1	2
HDA	none	22	23	20	21
GBIF	none	6	7	4	5

Fix the routing table, considering that NB IOAPIC starts at interrupt 24.

BUG=b:74104946
TEST=Build and boot to a modified grunt board to enable the emmc. Then used
"cat /proc/interrupts" to get active interrupts. Also checked IOAPIC
redirection registers, which are now being programmed.

Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Richard Spiegel 2018-04-03 08:51:48 -07:00 committed by Martin Roth
parent 0beb62760d
commit 48e074975d
1 changed files with 54 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

106
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl
View File

@ -29,15 +29,17 @@ Name (PR0, Package()
/* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */ /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */
/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
Package() { 0x0001FFFF, 0, INTB, 0 }, Package() { 0x0001FFFF, 0, INTG, 0 },
Package() { 0x0001FFFF, 1, INTC, 0 }, Package() { 0x0001FFFF, 1, INTH, 0 },
Package() { 0x0001FFFF, 2, INTE, 0 },
Package() { 0x0001FFFF, 3, INTF, 0 },
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Package() { 0x0002FFFF, 0, INTC, 0 }, Package() { 0x0002FFFF, 0, INTH, 0 },
Package() { 0x0002FFFF, 1, INTD, 0 }, Package() { 0x0002FFFF, 1, INTA, 0 },
Package() { 0x0002FFFF, 2, INTA, 0 }, Package() { 0x0002FFFF, 2, INTB, 0 },
Package() { 0x0002FFFF, 3, INTB, 0 }, Package() { 0x0002FFFF, 3, INTC, 0 },
/* FCH devices */ /* FCH devices */
/* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */
@ -48,11 +50,9 @@ Name (PR0, Package()
/* Bus 0, Dev 18 Func 0 - USB: EHCI */ /* Bus 0, Dev 18 Func 0 - USB: EHCI */
Package() { 0x0012FFFF, 0, INTC, 0 }, Package() { 0x0012FFFF, 0, INTC, 0 },
Package() { 0x0012FFFF, 1, INTB, 0 },
/* Bus 0, Dev 10 Func 0 - USB: xHCI */ /* Bus 0, Dev 10 Func 0 - USB: xHCI */
Package() { 0x0010FFFF, 0, INTC, 0 }, Package() { 0x0010FFFF, 0, INTC, 0 },
Package() { 0x0010FFFF, 1, INTB, 0 },
/* Bus 0, Dev 17 - SATA controller */ /* Bus 0, Dev 17 - SATA controller */
Package() { 0x0011FFFF, 0, INTD, 0 }, Package() { 0x0011FFFF, 0, INTD, 0 },
@ -65,14 +65,18 @@ Name (APR0, Package()
/* Bus 0, Dev 0 - F15 Host Controller */ /* Bus 0, Dev 0 - F15 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package() { 0x0001FFFF, 0, 0, 43 }, /* IOAPIC2BASE + (group * 4) == 24 + (1 * 4), CDAB swizzle */
Package() { 0x0001FFFF, 1, 0, 40 }, Package() { 0x0001FFFF, 0, 0, 30 },
Package() { 0x0001FFFF, 1, 0, 31 },
Package() { 0x0001FFFF, 1, 0, 28 },
Package() { 0x0001FFFF, 1, 0, 29 },
/* Bus 0, Dev 2 - PCIe Bridges */ /* Bus 0, Dev 2 - PCIe Bridges */
Package() { 0x0002FFFF, 0, 0, 44 }, /* IOAPIC2BASE + 23 */
Package() { 0x0002FFFF, 1, 0, 45 }, Package() { 0x0002FFFF, 0, 0, 47 },
Package() { 0x0002FFFF, 2, 0, 46 }, Package() { 0x0002FFFF, 1, 0, 48 },
Package() { 0x0002FFFF, 3, 0, 47 }, Package() { 0x0002FFFF, 2, 0, 49 },
Package() { 0x0002FFFF, 3, 0, 50 },
/* SB devices in APIC mode */ /* SB devices in APIC mode */
/* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */
@ -83,11 +87,9 @@ Name (APR0, Package()
/* Bus 0, Dev 18 Func 0 - USB: EHCI */ /* Bus 0, Dev 18 Func 0 - USB: EHCI */
Package() { 0x0012FFFF, 0, 0, 18 }, Package() { 0x0012FFFF, 0, 0, 18 },
Package() { 0x0012FFFF, 1, 0, 17 },
/* Bus 0, Dev 10 Func 0 - USB: xHCI */ /* Bus 0, Dev 10 Func 0 - USB: xHCI */
Package() { 0x0010FFFF, 0, 0, 18}, Package() { 0x0010FFFF, 0, 0, 18},
Package() { 0x0010FFFF, 1, 0, 17},
/* Bus 0, Dev 17 - SATA controller */ /* Bus 0, Dev 17 - SATA controller */
Package() { 0x0011FFFF, 0, 0, 19 }, Package() { 0x0011FFFF, 0, 0, 19 },
@ -103,7 +105,7 @@ Name (PS4, Package()
Package() { 0x0000FFFF, 3, INTD, 0 }, Package() { 0x0000FFFF, 3, INTD, 0 },
}) })
Name (APS4, Package() Name (APS4, Package()
{ { /* IOAPIC2BASE + (group * 4) == 24 + (0 * 4), no swizzle */
/* PCIe slot - Hooked to PCIe slot 4 */ /* PCIe slot - Hooked to PCIe slot 4 */
Package() { 0x0000FFFF, 0, 0, 24 }, Package() { 0x0000FFFF, 0, 0, 24 },
Package() { 0x0000FFFF, 1, 0, 25 }, Package() { 0x0000FFFF, 1, 0, 25 },
@ -114,49 +116,49 @@ Name (APS4, Package()
/* GPP 1 */ /* GPP 1 */
Name (PS5, Package() Name (PS5, Package()
{ {
Package() { 0x0000FFFF, 0, INTB, 0 }, Package() { 0x0000FFFF, 0, INTA, 0 },
Package() { 0x0000FFFF, 1, INTC, 0 }, Package() { 0x0000FFFF, 1, INTB, 0 },
Package() { 0x0000FFFF, 2, INTD, 0 }, Package() { 0x0000FFFF, 2, INTC, 0 },
Package() { 0x0000FFFF, 3, INTA, 0 }, Package() { 0x0000FFFF, 3, INTD, 0 },
}) })
Name (APS5, Package() Name (APS5, Package()
{ { /* IOAPIC2BASE + (group * 4) == 24 + (2 * 4), no swizzle */
Package() { 0x0000FFFF, 0, 0, 28 },
Package() { 0x0000FFFF, 1, 0, 29 },
Package() { 0x0000FFFF, 2, 0, 30 },
Package() { 0x0000FFFF, 3, 0, 31 },
})
/* GPP 2 */
Name (PS6, Package()
{
Package() { 0x0000FFFF, 0, INTC, 0 },
Package() { 0x0000FFFF, 1, INTD, 0 },
Package() { 0x0000FFFF, 2, INTA, 0 },
Package() { 0x0000FFFF, 3, INTB, 0 },
})
Name (APS6, Package()
{
Package() { 0x0000FFFF, 0, 0, 32 }, Package() { 0x0000FFFF, 0, 0, 32 },
Package() { 0x0000FFFF, 1, 0, 33 }, Package() { 0x0000FFFF, 1, 0, 33 },
Package() { 0x0000FFFF, 2, 0, 34 }, Package() { 0x0000FFFF, 2, 0, 34 },
Package() { 0x0000FFFF, 3, 0, 35 }, Package() { 0x0000FFFF, 3, 0, 35 },
}) })
/* GPP 2 */
Name (PS6, Package()
{
Package() { 0x0000FFFF, 0, INTA, 0 },
Package() { 0x0000FFFF, 1, INTB, 0 },
Package() { 0x0000FFFF, 2, INTC, 0 },
Package() { 0x0000FFFF, 3, INTD, 0 },
})
Name (APS6, Package()
{ /* IOAPIC2BASE + (group * 4) == 24 + (4 * 4), no swizzle */
Package() { 0x0000FFFF, 0, 0, 40 },
Package() { 0x0000FFFF, 1, 0, 41 },
Package() { 0x0000FFFF, 2, 0, 42 },
Package() { 0x0000FFFF, 3, 0, 43 },
})
/* GPP 3 */ /* GPP 3 */
Name (PS7, Package() Name (PS7, Package()
{ {
Package() { 0x0000FFFF, 0, INTD, 0 }, Package() { 0x0000FFFF, 0, INTA, 0 },
Package() { 0x0000FFFF, 1, INTA, 0 }, Package() { 0x0000FFFF, 1, INTB, 0 },
Package() { 0x0000FFFF, 2, INTB, 0 }, Package() { 0x0000FFFF, 2, INTC, 0 },
Package() { 0x0000FFFF, 3, INTC, 0 }, Package() { 0x0000FFFF, 3, INTD, 0 },
}) })
Name (APS7, Package() Name (APS7, Package()
{ { /* IOAPIC2BASE + (group * 4) == 24 + (6 * 4), no swizzle */
Package() { 0x0000FFFF, 0, 0, 36 }, Package() { 0x0000FFFF, 0, 0, 48 },
Package() { 0x0000FFFF, 1, 0, 37 }, Package() { 0x0000FFFF, 1, 0, 49 },
Package() { 0x0000FFFF, 2, 0, 38 }, Package() { 0x0000FFFF, 2, 0, 50 },
Package() { 0x0000FFFF, 3, 0, 39 }, Package() { 0x0000FFFF, 3, 0, 51 },
}) })
/* GPP 4 */ /* GPP 4 */
@ -167,9 +169,9 @@ Name(PS8, Package(){
Package(){0x0000FFFF, 3, INTD, 0 }, Package(){0x0000FFFF, 3, INTD, 0 },
}) })
Name (APS8, Package() Name (APS8, Package()
{ { /* IOAPIC2BASE + (group * 4) == 24 + (0 * 4), DABC swizzle */
Package() { 0x0000FFFF, 0, 0, 40 }, Package() { 0x0000FFFF, 0, 0, 27 },
Package() { 0x0000FFFF, 1, 0, 41 }, Package() { 0x0000FFFF, 1, 0, 24 },
Package() { 0x0000FFFF, 2, 0, 42 }, Package() { 0x0000FFFF, 2, 0, 25 },
Package() { 0x0000FFFF, 3, 0, 43 }, Package() { 0x0000FFFF, 3, 0, 26 },
}) })