mb/google/nissa/var/nivviks: Disable PCIe WLAN pins
Nivviks uses CNVi WLAN, so disable the PCIe-related GPIOs. BUG=b:218929856 TEST=Boot to OS on nivviks and check that WLAN still works. Change-Id: I68f12490b0f09658e1307828b0e4488504f50e61 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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@ -8,6 +8,10 @@
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/* Pad configuration in ramstage for nivviks board_id = 0 */
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static const struct pad_config board_id0_overrides[] = {
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/* D7 : WLAN_CLKREQ_ODL */
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PAD_NC(GPP_D7, NONE),
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/* H3 : WLAN_PCIE_WAKE_ODL */
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PAD_NC(GPP_H3, NONE),
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/* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
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/* R5 : I2S2_SFRM ==> I2S_SPK_LRCK_R */
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@ -30,18 +34,30 @@ static const struct pad_config board_id0_overrides[] = {
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
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};
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/* Pad configuration in ramstage for nivviks board_id >= 1 */
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static const struct pad_config override_gpio_table[] = {
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/* D7 : WLAN_CLKREQ_ODL */
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PAD_NC(GPP_D7, NONE),
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/* H3 : WLAN_PCIE_WAKE_ODL */
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PAD_NC(GPP_H3, NONE),
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};
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/* Pad configuration in ramstage for nirwen */
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static const struct pad_config override_gpio_table_nirwen[] = {
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/* B4 : SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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/* D7 : WLAN_CLKREQ_ODL */
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PAD_NC(GPP_D7, NONE),
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/* D11 : EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_D11, 1, DEEP),
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/* E13 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO(GPP_E13, 1, DEEP),
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/* E17 : SSD_PLN_L */
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PAD_CFG_GPO(GPP_E17, 1, PLTRST),
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/* H3 : WLAN_PCIE_WAKE_ODL */
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PAD_NC(GPP_H3, NONE),
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};
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/* Early pad configuration in bootblock for nivviks */
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@ -116,8 +132,8 @@ const struct pad_config *variant_gpio_override_table(size_t *num)
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}
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if (id == 1) {
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*num = 0;
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return NULL;
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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/* board_id >= 2 means nirwen */
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