soc/amd/stoney: clean up and update reset.c

- Move #defines to soc/northbridge.h, add other reset definitions to
soc/southbridge.h.
- Clean up file to use definitions instead of magic numbers.
- Add do_soft_reset()

BUG=b:69224851
TEST=Build gardenia; Build & boot Kahlee

Change-Id: I0cc4c04b53b7fec38d45e962ff1292d8c717269c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22439
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/soc/amd/stoneyridge/Makefile.inc

@@ -42,6 +42,8 @@ bootblock-y += BiosCallOuts.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += early_setup.c
 bootblock-y += pmutil.c
+bootblock-y += reset.c
+bootblock-y += sb_util.c
 bootblock-y += tsc_freq.c
 
 romstage-y += BiosCallOuts.c
@@ -51,6 +53,8 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 romstage-y += gpio.c
 romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
 romstage-y += pmutil.c
+romstage-y += reset.c
+romstage-y += sb_util.c
 romstage-y += smbus.c
 romstage-y += smbus_spd.c
 romstage-y += ramtop.c

src/soc/amd/stoneyridge/include/soc/northbridge.h

@@ -24,6 +24,8 @@
 #define D18F0_NODE_ID		0x60
 #define D18F0_CPU_CNT		0x62 /* BKDG defines as a field in DWORD 0x60 */
 # define CPU_CNT_MASK		0x1f /*  CpuCnt + 1 = no. CPUs */
+#define HT_INIT_CONTROL		0x6c
+# define HTIC_BIOSR_DETECT	((1 << 5) | (1 << 9) | (1 << 10))
 
 /* D18F1 - Address Map Registers */
 

src/soc/amd/stoneyridge/include/soc/southbridge.h

@@ -259,6 +259,15 @@
 
 #define FCH_MISC_REG40_OSCOUT1_EN	BIT(2)
 
+/* IO 0xcf9 - Reset control port*/
+#define   FULL_RST			BIT(3)
+#define   RST_CMD			BIT(2)
+#define   SYS_RST			BIT(1)
+
+/* PMx10 - Power Reset Config */
+#define PWR_RESET_CFG			0x10
+#define   TOGGLE_ALL_PWR_GOOD		BIT(1)
+
 static inline int sb_sata_enable(void)
 {
 	/* True if IDE or AHCI. */

src/soc/amd/stoneyridge/reset.c

@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2017 Google, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,34 +14,35 @@
  * GNU General Public License for more details.
  */
 
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
 #include <arch/io.h>
 #include <reset.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 
-#define HT_INIT_CONTROL			0x6c
- #define HTIC_BIOSR_Detect		(1 << 5)
-
-
-static void set_bios_reset(void)
+/* Clear bits 5, 9 & 10, used to signal the reset type */
+static void clear_bios_reset(void)
 {
 	u32 htic;
-	htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
-	htic &= ~HTIC_BIOSR_Detect;
-	pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+	htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
+	htic &= ~HTIC_BIOSR_DETECT;
+	pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
 }
 
 void do_hard_reset(void)
 {
-	set_bios_reset();
-	/* Try rebooting through port 0xcf9 */
-	/*
-	 * Actually it is not a real hard_reset
-	 *  --- it only reset coherent link table,
-	 *  but not reset link freq and width
-	 */
-	outb((0 << 3) | (0 << 2) | (1 << 1), SYS_RESET);
-	outb((0 << 3) | (1 << 2) | (1 << 1), SYS_RESET);
+	clear_bios_reset();
+
+	/* De-assert and then assert all PwrGood signals on CF9 reset. */
+	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
+		TOGGLE_ALL_PWR_GOOD);
+	outb(RST_CMD | SYS_RST, SYS_RESET);
+}
+
+void do_soft_reset(void)
+{
+	clear_bios_reset();
+
+	/* Assert reset signals only. */
+	outb(RST_CMD | SYS_RST, SYS_RESET);
 }